View AT76C713_717078.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

atmel confidential features ? advanced risc architecture, 130 powerful instructions, most single-clock cycle execution clock generator provides cpu rates up to 48 mhz only one external clock crystal of 12 mhz can generate all the required system clocks: ? internal clock for standard uart rates ? a 48 mhz and 96 mhz clock for usb data recovery ? avr processor and system clock full-speed usb interf ace (12 mbits per second) 2.0 compliant jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities a ccording to the jtag standard ? extensive on-chip debug support two on-chip 16550 uarts supporti ng baud rates up to 921 kbaud ? both uarts incorporate in dividual transmit and r eceive fifos of 16 bytes ? uart0 supports modem control signals programmable spi interface on-chip bootstrap rom provides a variety of firmware upgrade modes ? device firmware upgrade through usb for the internal program sram (no external non-volatile spi memory required) ? device firmware upgrade through usb fo r both the internal program sram and the external spi dataflash ? or eeprom ? spi program mode from the external dataflash or eeprom external memory interface su pporting up to 32 kbytes of external ram in address multiplexed mode, 2 banks of 256 bytes in non-multiplexed mode, fifo, or with an extra 20 gpios dma channels allow fast data transfers be tween endpoint buffers and internal or external sram (dma transfer ra te is 12 mhz for all channels) 8k x 16 bits (up to 11k x 16 bits), in-syst em sram for program code (program memory) on-chip 8 kbytes sram for data and variabl es (2, 4, or 6 kbytes can be remapped for program storage in the address area above the program memory two 8-bit timer/counters one 16-bit timer/counter four external interrupts through gpios programmable watchdog timer low voltage operation: ? 1.8v for the core ? 1.8v or 3.3v for the periphery ?3.3v for the usb 100-pin tqfp package applications ? programmable usb-to-serial bridge for rs-2332 devices (cell phones, printers, pdas, etc.) ? irda control over usb ? usb memory sticks ? general high-speed micr ocontroller application high-speed (48 mhz) avr ? microcontroller with usb interface AT76C713 5665b?usb?04/05
2 5665b?usb?04/05 AT76C713 atmel confidential 1. overview the AT76C713 is a low-power, high performing us b 2.0 full-speed microcontroller providing advanced features for usb peripherals. it combines a number of functions required in such a device, including the following: the device is based on the avr-enhanced risc architecture core, which combines an advanced instruction set with 32 general-purpose working registers. by executing powerful instructions in a single clock cycle, the at 76c713 achieves throughp uts approaching 1 mips per mhz, allowing the system designer to opti mize the power consumption versus the process- ing speed the clock generation circuit requires a clock input of 12 mhz and provides standard clock rates for the usb module and the on-chip uarts, as well as several avr cpu rates varying from 16 mhz up to 48 mhz internal dma channels allow fast data transfers between the usb buffers and the external or the on-chip memory without processor interruption. usb dma transfers use devoted data paths with a 12 mbytes transfer rate an on-chip flexible memory controller allows dynamic memory mapping and provides the required timing for interfacing with slow or fast external memory devices, like sram or fifos five multipurpose i/o ports, port(a-e), provide the signals for all the serial and parallel inter- faces. programmable strobe signals are provided for external fifo access. in addition, the AT76C713 supports various power-down modes and o ffers four external interrupts, a program- mable watchdog timer, and flexible timer/counters with compare modes on power-up, the bootstrap code is executed from the boot rom. the purpose of the bootstrap code is to load the application code into the pr ogram memory. the application code is executed from the on-chip sram program memory, contribu ting to the low-power consumption. different programming modes are supported, depending on the application (that is, the mode is selected externally by the pmode0 and pmode1 pins) in the slave programming mode, an external system (that is, the ho st), operating as spi master, can transfer the program image in a raw format to the program memory of the device. in this case, the AT76C713 operates as an spi slave and starts running from the internal boot rom code, which switches to the start of program memory when it detects the end of a valid program transfer from the host to the AT76C713 in the master programming mode, the AT76C713 reads the whole program image from an exter- nal serial eeprom or dataflash ? and switches to the start of the program memory when it completes this reading. alternatively, the AT76C713 reads only configuration parameters from a small serial non-volatile memo ry (eeprom or dataflash), ena bles the usb controller, and executes the usb device firmware upgrade (d fu) code that is stored in the boot rom the usb controller consists of a serial interfac e engine (sie), a function interface unit (fiu), and a system interface (si). the sie performs bit processing, line coding, packet generation, packet type recognition, serial-parallel data conversion, and packet delineation. the fiu con- sists of a protocol engine and a usb device with one control endpoint (ep0) and four programmable endpoints with up to 512 bytes maximum total size. all endpoints support double buffering in order to provide the maximum performance specified for the usb the AT76C713 supports two 16550 uart modules with 16 bytes fifos in each direction. the uart0 serial interface provides full modem cont rol functionality with the rts/cts, dtr/dsr, ri, and cd signals. these signals are provided by the general-purpose i/o pins of portd
3 5665b?usb?04/05 AT76C713 atmel confidential the AT76C713 avr is supported with a full suite of program and system development tools, including: c compiler, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits 2. AT76C713 functional diagram pm1 nrst pb4/nss pd0/sin0 pd1/sout0 pd2/ rts pd3/cts pd4/dsr pd5/ dtr pd6/cd pd7/ri pe0 /sin1 pe1/sout1 pe2/int0 pe3/int1 pe4/int2 pe5/int3 pe6/nwr pe7/nrd nfwr susp nfrd ncs[0:1] usb_attach dp, dm tck tdi tdo boot rom 8kx16bits sram program memory controller uart0 wd timer timers clock generator register file sram av r core dma controller uart1 memory mapped modules i/o mapped modules memory controller lft spi controller fifos usb controller fifos irda 1.0 port interface boundary scan chain (jtag) jtag tap ocd 8kbytes testen test_ck tms xin xout pm0 pa[7:0]/ad[7:0] pb0/t0 pb1/t1 pb2/t2 pb3/icp pb5/mosi pb6/miso pb7/sck pc[7:0]/a[14:8], ale/a[7:0]
4 5665b?usb?04/05 AT76C713 atmel confidential 3. pin diagram 3.1 100-pin tqfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 n/c n/c pgnd nrst cvdd pe7/nrd pe6/nwr pe5/nint3 pe4/nint2 pe3/nint1 pe2/nint0 pe1/sout1 pe0/sin1 pvdd pmode0 pmode1 cgnd pgnd lft pagnd xin xout pavdd n/c pavdd pagnd vext por_vsel pvdd pc7/ale pc6/a14 pc5/a13 cgnd pc4/a12 pc3/a11 pc2/a10 pc1/a9 pc0/a8 cvdd pb7/sck pb6/miso pb5/mosi pb4/nss pb3/icp pb2/t2 pvdd pgnd n/c n/c pvdd pvdd n/c pa 3 pa 4 pa 5 pa 6 pa 7 pvdd_usb dm dp susp cgnd pgnd cvdd pd0/sin0 pd1/sout0 pd2/rts pd3/cts pd4/dsr pd5/dtr pd6/cd pd7/ri pvdd_portd n/c pgnd n/c n/c pvdd test_clk test_en pb0/t0 pb1/t1 pa 0 pa 1 pa 2 cvdd nfrd nfwr ncs0 ncs1 cgnd js_tdo js_tdi js_tms js_tck usb_attach pvdd pgnd n/c pgnd
5 5665b?usb?04/05 AT76C713 atmel confidential 4. pin summary ? pin assignment table 4-1. pin summary ? pin assignment pin # pin name pin # pin name pin # pin name 1 n/c 35 pc3/a11 69 pa7 2 n/c 36 pc2/a10 70 pa6 3pgnd 37pc1/a9 71pa5 4 nrst 38 pc0/a8 72 pa4 5 cvdd 39 cvdd 73 pa3 6 pe7/nrd 40 pb7/sck 74 n/c 7 pe6/nwr 41 pb6/miso 75 pvdd 8 pe5/nint3 42 pb5/mosi 76 pgnd 9 pe4/nint2 43 pb4/nss 77 n/c 10 pe3/nint1 44 pb3/icp 78 pgnd 11 pe2/nint0 45 pb2/t2 79 pvdd 12 pe1/sout1 46 pvdd 80 usb_attach 13 pe0/sin1 47 pgnd 81 tck 14 pvdd 48 n/c 82 tms 15 pmode0 49 n/c 83 tdi 16 pmode1 50 pvdd 84 tdo 17 cgnd 51 pgnd 85 cgnd 18 pgnd 52 n/c 86 ncs1 19 lft 53 pvdd_portd 87 ncs0 20 pagnd 54 pd7/ri 88 nfwr 21 xin 55 pd6/cd 89 nfrd 22 xout 56 pd5/dtr 90 cvdd 2 3 pav d d 5 7 p d 4 / d s r 9 1 pa 2 24 n/c 58 pd3/cts 92 pa1 2 5 pav d d 5 9 p d 2 / rt s 9 3 pa 0 26 pagnd 60 pd1/sout0 94 pb1/t1 27 vext 61 pd0/sin0 95 pb0/t0 28 por_vsel 62 cvdd 96 test_en 29 pvdd 63 pgnd 97 test_clk 30 pc7/ale 64 cgnd 98 pvdd 31 pc6/a14 65 susp 99 n/c 32 pc5/a13 66 dp 100 n/c 33 cgnd 67 dm 34 pc4/a12 68 pvdd_usb
6 5665b?usb?04/05 AT76C713 atmel confidential 5. signal description table 5-1. signal description type: i = input, o = output, i/o = bi-directional, a = analog signal name type description jtag signals tck i jtag clock input tdi i scan chain bitstream input tdo o scan chain bitstream output tms i jtag mode select input port signals pa[0:7] b port a is used in configurations with external memo ry, where it acts as the ad0-7 address and/or data bus. if the alternative function of the port is not used, port a also serves as an 8-bit bi-directional i/o port with internal pull-up resistors. port a output buffers can si nk 20 ma and can drive the led displays directly. port a pins that are externally pulled low will source current . the port a pins are inputs when a reset condition becomes active, even if the clock is not running. pb[0:7] b the high nibble of port b (pb[7?4]) offers the signals fo r the spi interface. the low-nibble (pb[3-0]) is used from the three internal timers as trigger and capt ure inputs. these functions can operate regardless the direction of the pb[3-0] pins. port b serves also as an 8-bit bi-directional i/o po rt with internal pull-up resistors, if the alternative functions of the port are not used. the port b output buffers can sink 20 ma and can drive led displays directly. as inputs, port b pins that are externally pu lled low will source current. the port b pins are inputs when a reset condition becomes active, even if the clock is not running. the alternative functions of port b are explained in more details at the following table and at the proper sections. pc[0:7] b port c is used in configurations with external me mory, where it acts as the address bus bits a8-15 and ale in a multiplexed address mode and a0-7 in a non-multiplexed mode. if the alternative functions of the por t are not used, port c also serves as an 8-bit bi-directional i/o port with internal pull-up resistors.the port c output buffers can sink 20 ma and can drive the led displays directly. port c pins that are externally pulled low will source current. the port c pins are inputs when a reset condition becomes active, even if the clock is not running. alternative functions of port b port alternate function pb0 t0: timer/counter 0 clock input pb1 t1: timer/counter 1 clock input pb2 t2: timer/counter 2 clock input pb3 icp1: input capture pin for timer/counter1 pb4 nss: spi slave port select input pb5 mosi: spi slave port select input pb6 miso: spi master data in, slave data out pb7 sck: spi master clock out, slave clock in
7 5665b?usb?04/05 AT76C713 atmel confidential pd[0:7] b port d offers the data and handshaking signals for uart0 interface, as listed below. when the uart0 is not used, port d is also an 8-bit bi-directional i/o port with internal pull-up resistors. the port d output buffers can sink 20 ma. port d pins that are externally pulled low will source current. the port d pins are inputs when a reset condition becomes active, even if the clock is not running. pe[0:7] b port e offers the data signals for the uart1 interface, offers 4 external interrupt lines (edge triggered or level sensitive external interrupt) and the nwr/nrd signals for configurations with external memory. if the alternative functions are not used, port e serves as an 8-bit bi-directional i/o port with internal pull- up/down resistors. pins pe2 and pe3 have pull-down re sistors while the rest pins have pull-up resistors. the output buffers of port e pads can sink 20 ma. port e pins that are externally pulled low (or high for pe2 and pe3 pins) will source current. the port e pi ns are inputs when a reset condition becomes active, even if the clock is not running. table 5-1. signal description (continued) type: i = input, o = output, i/o = bi-directional, a = analog signal name type description alternative functions of port d port alternate function pd0 sin0, serial in uart0 (i): this pin provides the serial receive data input to uart0 pd1 sout0, serial out uart0 (o): this pin provides the serial transmit data from the uart0 pd2 nrts, ready to send (b): rts uart0 handshaking signal pd3 ncts, clear to send (b): cts uart0 handshaking signal pd4 ndsr, data set ready (b): dsr uart0 handshaking signal pd5 ndtr, data terminal ready (b): dtr uart0 handshaking signal pd6 ncd, carrier detect (b): cd uart0 handshaking signal pd7 nri, ring indicator (b): ri uart0 handshaking signal alternative functions of port e port alternate function pe0 sin1, serial in uart1 (i): this pin provides the serial receive data input to uart1. pe1 sout1, serial out uart1 (o): this pin provides the serial transmit data from the uart1 pe2 int0, edge-triggered or level sensitive interrupt with pull-down pe3 int1, edge-triggered or level sensitive interrupt with pull-down pe4 int2, edge-triggered or level sensitive interrupt with pull-up pe5 int3, edge-triggered or level sensitive interrupt with pull-up pe6 nwr pe7 nrd
8 5665b?usb?04/05 AT76C713 atmel confidential usb serial interface dp i/o usb data i/o (positive differential line). dp and dm form the differential signal pin pair connected to the host controller or an upstream hub. dm i/o usb data i/o (negative differential line) usb_attach o this output controls the pullu p resistor of the dp signal. when low, it enforces the host to re-enumerate the device. programming mode control signals pmode0 pmode1 i pmode0 and pmode1 pins are used from the on- chip bootstrap code and define the programming mode. for more details refer to the program modes section. test signals test_en i general-purpose signal for test. tied to v ss in normal conditions. test_clk i used only for production setting. tied to v ss in normal conditions. por_vsel i used in production phase only. tied to v ss in normal conditions. vext i used in production phase only. tied to 1.8v in normal conditions. other signals nrst i reset input. a low on this pin for two clock cycles while the oscillator is running resets the device. note that there is no internal pull-up resistor on this pin. susp o indicates if the ic is in power down mode ncs0 o external memory chip select 0 ncs1 o external memory chip select 1 nfwr o external fifo write nfrd o external fifo readl xin i system clock oscillator pad, input to the inverting o scillator amplifier and input to the internal system clock operating circuit. xout o system clock oscillator pad, output from the inverting oscillator amplifier. lft a an external rc filter should be connected to this pin to stabilize the lock-in time of the internal pll for the master clock input xin.main pll lft input power supply pins cgnd power 0 volts supply to the core cvdd power 1.8 volts supply to the core pgnd power 0 volts supply to the external section of the i/o circuitry pvdd power 1.8v or 3.3 volts supply to the external section of the i/o circuitry pvdd_portd power 1.8v or 3.3 volts supply to the external section of the port d i/o circuitry pvdd_usb power 3.3 volts supply for the usb and suspend pins pagnd power 0 volts analog supply to the core, ac and dc sections of the i/o circuitry pavdd power 1.8 volts analog supply to the core, ac and dc sections of the i/o circuitry table 5-1. signal description (continued) type: i = input, o = output, i/o = bi-directional, a = analog signal name type description
9 5665b?usb?04/05 AT76C713 atmel confidential 6. functional description 6.1 bootstrap rom and programming modes the bootstrap code in the boot rom of the AT76C713 is always activated on power-up or after a system reset. the functionality of the bootstra p code is configured by pins pmode0 and pmode1. in the spi master programming modes, the AT76C713 is master over the spi inter- face and can support an extern al eeprom or dataflash. the spi slave programming mode is useful in a system where an external hos t is present and keeps the image code for the AT76C713 in its own memory. 6.1.1 usb dfu-only mode when both the pmode0 and pmode1 pins are ti ed low, the bootstrap code will not enable the usb controller but not the spi co ntroller. the system will wait for a usb dfu sequence using the default usb descriptors stored in the boot rom. 6.1.2 slave programmming mode when the pmode0 pin is tied low and the pmode1 pin is tied high, the bootstrap rom config- ures the spi as a slave and waits for a specific sequence of data through the spi. the sequence is as follows 1. the nss pin is enabled. 2. the configuration header (256 bytes) is transmitted. 3. image of the code to be stored in program memory is transmitted, starting from address 0. (the code size is determined in the configuration header.) 4. the nss pin is disabled and re-enabled. 5. confirmation byte 1 is transmitted. 6. confirmation byte 2 is transmitted. 7. the nss pin is disabled table 6-1. programming modes pmode0 pmode1 programming mode 0 0 usb dfu only (spi disabled) 0 1 spi slave: spi master host must be present 1 0 spi master: spi serial eeprom is assumed 1 1 spi master: spi dataflash is assumed
10 5665b?usb?04/05 AT76C713 atmel confidential figure 6-1. slave programming mode sequence during the transmission of the configuratio n data and code image, the AT76C713 returns an 8- bit counter value that counts the received bytes. thus, the host can verify if the AT76C713 has received the correct amount of data. during the first confirmation cycle, the spi master sends $ca to command ?continue analyzing? or $ab to command ?abor t?. the spi slave will return ?data was ok? by sendin g $d0 or ?error? by sending $ee. during the second confirmation cycle, the spi master data is ignored and the spi slave sends the positive acknowledgment $ad ?analyzing data?, or one of the following error messages: $dd ?discarding data?, $de ?discarding due to transmission error?, or $ee ?error in confirmation command?. if the slave programming sequen ce fails, then the AT76C713 will enable the usb controller wait- ing for the dfu sequence, using the default usb descriptors. 6.1.3 master programming modes when the pmode0 pin is tied high, the bootstrap rom configures the spi as a master and is prepared to communicate either with a serial eeprom if pmode1 is tied low, or with a dataflash if pmode1 is tied high. the at76 c713 supports any atmel eeprom of the at25xxx type (for example, at25040) an d dataflash of the at45xxx type. the first 256 bytes that are read by the eeprom or dataflash are known as the configuration header, which contains useful information for the rest of the downloading procedure. the bytes fetched from the external serial memory may be an image code or configuration parameters. if the bytes are an image code, after data fetching is complete the program running in the boot rom resets the avr program counter and switches to the sram program memory by setting the remap bit in the memory access interface. table 6-2. possible cases of programming during the slave program mode case 1234 cycle 1 master $ca $ab xx invalid slave $d0 $d0 $ee xx cycle 2 master xx xx xx xx slave $ad $dd $de $ee programming ok fail fail fail mosi nss miso c1 c2 c1 c2 confirmation data transfer configuration config. header image code data (8-bit received data counter)
11 5665b?usb?04/05 AT76C713 atmel confidential if the data fetched from the external serial me mory is configuration parameters only, the boot- strap code of the boot rom will not switch to the program memory at the end of data fetching. instead, it will enable the usb controller. the usb will enumerate using the descriptors loaded from the spi memory. upon enumeration completion , if a dfu application is enabled in the host, then the bootstrap rom will support program storing in the program memory through the usb. when program storing is co mplete, the device will switch to the program memory. 6.1.4 configuration header the configuration header is at least 256 byte s length and consumes the first page of the spi memory. for systems that use spi slave progra mming or spi eeprom memory (for example, at25128a), the configuration header length is fixed to 256 bytes. for systems that use spi dataflash, the page size is equal to the page si ze of the used dataflash. for example, using the at45db011b, the page size is 264 bytes and t hus, the configuration header will consume 264 bytes. the meaning of each byte is described in table 6-3 . the first 2 bytes must be $55 and $aa in order to detect the rest of the information as valid. if those bytes are invalid, then the bootstrap code rejects the operation immediately and starts the usb dfu procedures. size[15:0] is the length of the image code counted in pages. during the slave programming mode and the spi eeprom master programmi ng mode, each page is 256 bytes long. the control bitmap (or control byte) is described in table 6-4 . table 6-3. configuration header byte description 0 $55 1$aa 2 size[7:0] 3 size[15:8] 4 control byte 5 memmap 6cis[ ] device descriptor configuration descriptor serial descriptor product descriptor table 6-4. control bitmap control byte bit field description 7 wsof wait usb sof. 6? reserved to zero (?0?). 5plck if set, then don?t use the pll lock signal (see also the plck bit of ?clock control register (clk_cntr)? on page 51 ).
12 5665b?usb?04/05 AT76C713 atmel confidential note: bits 7, 3, 2, 1 and 0 affect only the bootstrap usb dfu process memmap byte will be assigned immediately to t he memmap register (see memmap descrip- tion in the ?memory access interface? on page 15 ). this register configures the size of the program memory and data memory. cis[ ] is a table that carries the usb descriptors. each descriptor starts right after the end of the previous one. the order is shown in table 6-3 . the remaining bytes from the end of the cis[ ] table up to the end of the page have no meaning. note: if the remap bit of the control byte is cleared, then the image code will be loaded into the AT76C713 program memory (see size[15:0]), the system will not remap, an d the bootstrap code will enable the usb core and enumerate using the new usb descriptors (cis[ ]) instead of the default usb descriptors. 6.2 avr core the AT76C713 chip is based on the avr core architecture. all peripherals, apart from spi, irda, and timers, are memory mapped to the data address space. 6.2.1 interrupt handling the interrupt vector table of the AT76C713 is shown in table 6-5 . 4 remap if set, then remap right after the downloading of the image code is successful. 3stdby if set, use for sleep state in suspend mode the stand-by mode instead of power- down mode. 2 intprot interrupt protect. 1 dtch detach enable: if set, detach before remap. 0 susp if set the suspend circuit is on. table 6-4. control bitmap control byte bit field description table 6-5. interrupt vector table of the AT76C713 vector number program address source interrupt definition 1 $0000 reset h/w pin and watchdog reset 2 $0002 susp_resm usb suspend and resume 3 $0004 usb usb h/w & usb dma interrupt 4 $0006 int0 external interrupt request 0 5 $0008 int1 external interrupt request 1 6 $000a int2 external interrupt request 2 7 $000c int3 external interrupt request 3 8 $000e timer2_ovf timer/counter2 overflow 9 $0010 timer1_capt timer/counter1 capture event 10 $0012 timer1_compa timer/counter1 compare match a 11 $0014 timer1_compb timer/counter1 compare match b
13 5665b?usb?04/05 AT76C713 atmel confidential note: the program memory word length is 16-bits wide. 6.3 oscillator and clock generator the AT76C713 clock generation circuit is based on a single clock input from an external 12 mhz crystal connected to the oscillator pad. all internal clocks are gene rated by multiplying this clock input incorporating an on-chip pll. the output of the pll can be configured in 96 mhz (default) or 192 mhz. in order to produce the desired clocks, the clock generator circuit divides the pll output. generating and then dividing a high frequency pll output reduces the impact of jitter imported by the pll. an elaborate gobbling circuit produces a 14.769 mhz clock from the pll output, which can sup- port all standard baud rates with an acceptable frequency error. figure 6-2. AT76C713 clock generation tree 6.3.1 pll lft pin figure 6-3 shows the circuit that must be attached to an lft pin. the circuit consists of r1 = 330 ? , c1 = 33nf, and c2 = 3.3nf. 12 $0016 timer1_ovf timer/counter1 overflow 13 $0018 timer0_ovf timer/counter0 overflow 14 $001a spi_stc spi serial transfer complete 15 $001c uart0_irq uart0 interrupt request 16 $001e uart1_irq uart1 interrupt request table 6-5. interrupt vector table of the AT76C713 vector number program address source interrupt definition o s c p l l xtal 1 2mhz /2 m u x 96 or 192m hz /32 96mhz /2 2/13 3mhz 48mhz 96mhz 14.769mhz /4 m u x /5 /6 delay m u x clk_cntr.osc_nslp clk_cntr.npcip clk_cntr.pivoc1 clk_cntr.mul16 clk_cntr.mul16 clk_cntr.plck pll lock clk_cntr.mcsp1.0 uarts usb wdt pll stable system (avr,etc)
14 5665b?usb?04/05 AT76C713 atmel confidential figure 6-3. lft pin circuit 6.4 memory map r1 c1 33nf c2 3.3nf lft 330 ohm module base address $0000 $0020 $0060 $0800 $1000 $1800 $2000 $f000 $f200 $f300 $f800 $ff00 $a000 description program memory controller memory access interface uart1 uart0 usb memory mapped peripherals external memory (application specific) external data memory internal sram bank 6,7 internal sram bank 0,1 internal sram bank 4,5 internal sram bank 2,3 i/o registers avr core registers max. internal data memory min. internal data memory registers
15 5665b?usb?04/05 AT76C713 atmel confidential 6.5 memory access interface the memory access interface consists of t he memory remapping interface and the external memory interface. 6.5.1 memory remapping interface on power-up, the device has 11k words (22k x 8) of program sram and 2 kbytes of data sram. utilizing the memmap regist er (allocated in $f800 data memory address), it is possible to resize the two memory spaces. the last three 2-kbyte banks of program memory can be reallo- cated and used as data memory and vice versa. according to table 6-7 , there are three possible options: 1. to remap the last 2 kbytes (data banks 6 and 7) 2. to remap the last 4 kbytes (data banks 4 to 7) 3. to remap the last 6 kbytes (data banks 2 to 7) figure 6-4 and table 6-7 illustrate the remapping. table 6-6. memory map address space size (bytes) module $ff00-$ff04 5 program memory controller (pmc) $f800-$f802 3 memory access interface $f300-$f30c 13 uart1 $f200-$f20c 13 uart0 $f000-$f0fd 254 usb (end of internal sram)-$7fff (application specific) external sram $1800-$1fff 2048 internal sram bank 3 $1000-$17ff 2048 internal sram bank 2 $0800-$0fff 2048 internal sram bank 1 $0060-$07ff 2048 internal sram bank 0 $0020-$005f 64 i/o registers $0000-$001f 32 avr registers
16 5665b?usb?04/05 AT76C713 atmel confidential figure 6-4. memory remapping 8 8k 8 8k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 8 1k 16 data sram bank 0,1 (dedicated) data sram bank 2,3 data sram bank 4,5 data sram bank 6,7 data memory program memory data memory 0 data memory 1 data memory 2 data memory 3 data memory 4 data memory 5 data memory 6 data memory 7 data memory 7 data memory 5 data memory 3 data memory 6 data memory 4 data memory 2 program memory 0 program memory 1 program sram bank 0,1 (dedicated) program sram bank 2, 3 (data sram bank 7, 6) program sram bank 4, 5 (data sram bank 5, 4) program sram bank 6, 7 (data sram bank 3, 2) table 6-7. memory map allocation cases data banks allocated to data memory space memmap register value data address space program address space 0 1 $0000-$07ff (2 kbytes) $8000-$d7ff (22 kbytes) 2 3 $0000-$0fff (4 kbytes) $8000-$cfff (20 kbytes) 4 5 $0000-$17ff (6 kbytes) $8000-$c7ff (18 kbytes) 6 7 $0000-$1fff (8 kbytes ) $8000-$bfff (16 kbytes)
17 5665b?usb?04/05 AT76C713 atmel confidential 6.5.2 external memory interface (emi) the external memory can have various configur ations and can be accessed by either the avr core or the usb dma co ntroller (see also the ?usb dma controller? on page 19 ). the periphen i/o register (emien bit) (see description on page 52 ) enables and disables the external memory interface. the registers that control the external memory access by the avr core are located in the i/o space and named emicra and emicrb. the registers that control the external memory access by the usb dma controller are located in the memory space and named dma_emicra, dma_emicrb. the bit position of the two register pairs, emicra with dma_emi cra and emicrb with dma_emicrb, are identical. the emd0/1 bits select the external memory interface mode, according to table 6-9 . there are three control signals related to the control bits: the read signal (nrd or nfrd) controlled by rw0/1 and rm0/1 bits the write signal (nwr or nfwr) controlled by ww0/1 and wm0/1 bits the address latch enable signal (ale) controlled by aw0/1 and am0/1 bits the rw0/1, ww0/1, and aw0/1 bits control the wait states inserted in the corresponding (read, write, and ale) signals. the rm0/1, wm0/1, and am0/1 bits control the mode (waveform) of the corresponding (read, write, and ale) signals. figure 6-5 shows the signal waveform as defined by the corresponding control bits xw0/1 and xm0/1, where ?x? can be ?r?, ?w?, or ?a? (for read, write, or ale signal). table 6-8. the emi registers register offset address function emicra $1c ($3c) controls the external memory access by the avr core dma_emicra ($f801) controls the external memory access by the usb dma controller emicrb $1d ($3d) controls the external memory access by the avr core dma_emicrb ($f802) controls the external memory access by the usb dma controller table 6-9. emdo/1 bits emd1 emd0 external memory interface mode 00 fifo 01 reserved 1 0 demultiplexed 1 1 multiplexed
18 5665b?usb?04/05 AT76C713 atmel confidential figure 6-5. the signal waveform of control bits xw0/1, xm0/1 note: ?ramadr[8]? is the address bit 8 of the internal avr data memory space. the external memory address bus is equal to the internal avr data address bus.the ncs0 (or ncs1) and the data bus are valid during the write cycle. during the read cycle, the ncs0 (or ncs1) is valid during the access cycle, while the data bus must be valid during the end of the cycle (rising edge of system clock, which causes the rising edge of ncs pin). figure 6-6 shows an example of the read and write accesses on a demultiplexed external mem- ory (emd1/0 = 10). the read cycle is defined with zero wait states (rw1/0 = 00) and waveform mode 01 (rm1/0 = 01). the write cycle is defined with one wait state (ww1/0 = 01) and wave- form mode 10 (wm1/0 = 10). table 6-10. the functionality of the ncs0 and ncs1 pins during an external memory access cycle external memory interface mode ramadr[8] ncs0 ncs1 fifo x 1 1 demux 001 demux 110 mux x 1 0 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 11 01 11 10 11 11 01234 wait cycles (xw0/1) mode (xm0/1) (reserved) (reserved) cpu cycles
19 5665b?usb?04/05 AT76C713 atmel confidential figure 6-6. example of read and write access on a demultiplexed external memory 6.6 usb dma controller the AT76C713 offers a flexible dma mechanism for fast data transfers between the endpoint buffers and the memory. using dma, the avr program is not occupied with data transfers and this results in the conservation of processing ti me. the dma controller is capable of moving data as fast as 12 mbytes per second. the usb dma controller has direct access to either internal or external data memory. when the usb starts a dma transfer to or from the data memory, then the dma controller prevents the avr from accessing the same data memory area (i nternal or external). during a dma transfer, the avr can access any of the general-purpose registers. once the avr performs an access to the data memory area where a dma transfer is occupied, the dma controller then imposes wait cycles to the avr until the dma transfer is complete. thus, no further improvement is required from the firmware to prevent external or internal memory access during the dma transfers. to enable a dma transfer, the following steps should be performed 1. program the offset address of the fifo data register of the associated endpoint (this is the address of the fdrx register, that is, $f0ce for fdr1 ) 2. program the number of the bytes to be moved to/from the fifo data register 3. enable the write or read dma cycle the avr must poll the usb in order to detect the dma completion. system clock ncs address bus read access cycle data bus nrd ncs address bus write access cycle data bus nwr
20 5665b?usb?04/05 AT76C713 atmel confidential 6.7 usb controller the usb controller contains its own internal regi ster file, which is memory mapped onto the avr data bus. the usb block implements the low-leve l processing functions of the usb protocol stack described in universal serial bus specification, version 1.1 and handles the data transfers between the endpoint (ep) fifos and the system memory. the usb controller consists of an sie, an fiu, and the si. figure 6-7. usb controller the usb controller supports one control endpoint and seven programmable endpoints in terms of the type (bulk, int, or iso) and the direction (in, out). the fiu includes the endpoint buff- ers and the controllers of endpoints shown in table 6-11 . a pair endpoint address scheme is also supported. according to this scheme, two endpoints may have the same address, provided one of the endpoints has been configured as in and the other as out. 6.7.1 usb system interface (si) the usb si is necessary to bridge the avr dat a bus with the usb controller because the sys- tem clock and the usb controll er clock are asynchronous. when the avr accesses the usb registers, the u sb system interface inserts wait cycles to the avr core in order to synchronize the da ta memory bus with the usb local bus. table 6-11. usb function interface unit structure endpoint type number of bytes buffer type endpoint 0 control 16 single endpoint 1..3 any 128 (2 x 64) double endpoint 4 any 64 single endpoints 5..7 any 0 single fifos fiu si sie dp dm usb controller avr memory bus
21 5665b?usb?04/05 AT76C713 atmel confidential 6.7.2 usb interrupt handling all interrupt signals from the usb functions (p rotocol handler) are consolidated into the usb interrupt line. the interrupt line from the usb pr otocol handler is then multiplexed with the indi- vidual interrupt signals generated internally, and a single interrupt output is provided to the system interrupt controller. all interrupts are masked through the interrupt enable registers that exist in the usb controller. the external resume and received resume interrupts are cleared when the firmware clears the interrupt bit. the suspend interrupt is automatica lly cleared when activity is detected. all other interrupts are cleared when the processor sets a corresponding bit in an interrupt acknowledge register in the usb macro cell. there is only one bit for each interrupt source. table 6-12 describes each of the interrupt sources of the usb protocol handler (see also the uisr register). 6.7.3 interrupt priority the usb macro interrupt priority is defined in table 6-13 . 6.7.4 endpoint interrupt endpoint interrupts are triggered by the setting or clearing of one or more bits in the control and status registers of an endpoint. these interrupt s are caused by events during packet transac- table 6-12. usb interrupt sources interrupt description function ep0 interrupt see control transfers at function ep0 for details function ep1 interrupt for an out endpoin,t it indicates that function endpoint1 has received a valid out packet and that the data is in the fifo. for an in endpoint, it means that the endpoint has rece ived an in token, sent out the data stored in the fifo, and received an ack from the host. the fifo is now ready to be written by new data from the processor function ep2 interrupt see function ep1 interrupt function ep3 interrupt see function ep1 interrupt function ep4 interrupt see function ep1 interrupt function ep5 interrupt see function ep1 interrupt function ep6 interrupt see function ep1 interrupt sof received the usb h/w decodes a valid start of frame ext rsm the h/w has received a remote wake-up request rcvd rsm the h/w has received resume signaling. the processor's firmware should take the function out of the suspended state susp the h/w has detected a suspend condit ion and is preparing to enter the suspend mode. the processor's firmware should place the embedded function in the suspend mode table 6-13. usb macro interrupt priority priority level interrupt name 2: high level sof received 1: same level (low level) function ep0 to ep6
22 5665b?usb?04/05 AT76C713 atmel confidential tions and are different for control and non-control endpoints. the interrupts are described below with respect to the control and status register bit definitions. 6.7.5 interrupt for non-control endpoints rx out packet set (0 -> 1) tx packet ready clear (1 -> 0) 6.7.6 interrupt for control endpoints rx out packet set (0 -> 1) rx setup set (0 -> 1) tx packet ready clear (1 -> 0) tx complete set (0 -> 1) 6.7.7 usb function interface (fiu) the fiu provides the interface between the processor (via the si) and the sie. it manages transactions at the packet level with minimal intervention from the processor, handles the end- points? fifos, monitors the status of the transactions and communicates with the avr through a set of status and control registers. the fiu is designed to operate in single-packet mode and to manage the usb packet protocol layer. to operate the fiu, the firmware must first enable the endpoints of the fiu, and then select a direction and ping-pong capability. once enabl ed, the endpoints are in receive mode by default. the fiu notifies the processor when a valid token has been received. the data con- tained in the data packet will be supplied in the fifo. the processor transfers the data to and from the host by interacting with each endpoint's fifo and control and status registers. for example, when transmitting an in packet, th e fiu assembles the data of the endpoint's fifo in a usb packet, transmits the packet, and then signals the processor after the host receives and acknowledges the packet. the fiu performs automatic data packet retransmission and data0/data1 pid toggling. for setup tokens, the processor must parse the device request and then respond appropri- ately. after a setup token, there may be 0 or more data in or data out packets for which the processor must either supply or receive the data. 6.7.8 usb serial interface engine (sie) the sie performs the following functions: nrzi data encoding/decoding bit stuffing/un-stuffing crc generation and checking acks and nacks identifying the type of a token address checking clock generation (via dpll) 6.7.9 control transfers at function ep0 legend: data1/data0 = data packet with data1 or data0 pid
23 5665b?usb?04/05 AT76C713 atmel confidential data 1 (0) = zero length data1 packet host usb macro microcontroller setup stage 1. [sync]-[setup] 2. [sync]-[data0] 3. data are put in fifo 4. if crc ok, send:[sync]-[ack] 5. if crc ok, set rx_setup bit 6. interrupt 7. read uisr (bit 0 is set) 8. read fcsr0 (rx_setup bit) 9. read fbyte_cnt0 10. read fifo 0 11. parse data if control read phase: set control direction clear rx_setup bit fill fifo with data set tx_packet_ready if control write phase: clear control direction clear rx_setup bit if no data stage phase: clear control direction set data_end bit set force_stall bit if unsupported command: set force_stall bit 12. set uiar (ep0 inta) status stage, no data stage 1. [sync]-[in] 2. send data1(0) 3. if crc ok, send [sync]-[ack] 4. set tx_complete bit 5. interrupt 6. read uisr 7. read csr
24 5665b?usb?04/05 AT76C713 atmel confidential 8. if set_address write device address to faddr set fadd enable bit of global state registe if set_configuration with a 1: set config bit of global state register 9. clear tx_complete bit 10. clear data_end bit 11. set force_stall bit 12. set uiar (ep0 inta) data stage, control read 1. [sync]-[in] 2. if tx_packet_ready = 1 send data0 / data1 else, send stall 3. if crc ok, send [sync]-[ack] 4. clear tx_packet_ready 5. set tx_complete bit 6. interrupt 7. read uisr 8. read csr 9. clear tx_complete bit 10. if more data fill fifo with data and set tx_packet_ready else if a null packet should be sent, set data_end and set tx_packet_ready else if all bytes sent and need to send a null packet, set data_end and set set_force_stall 11. set uiar (ep0 inta) status/early status stage with read data stage 1. [sync]-[out] host usb macro microcontroller
25 5665b?usb?04/05 AT76C713 atmel confidential 2. [sync]-[data1(0)] 3. if tx_complete = 0 then send [sync]-[ack] and set rx_out else send [sync]-[nack] 4. interrupt 5. read uisr 6. read csr 7. clear rx-out 8. set data_end 9. set force_stall comment: a setup token will clear data_end. not cleared by firmware in case host retries 1 through 3 10. 11. set uiar (ep0 inta) data stage, control write 1. [sync]-[out] 2. [sync]- [ data 1 / data 0 ] 3. data are put in fifo 4. if crc ok send [sync]- [ack] 5. if crc ok, set rx_out 6. interrupt 7. read uisr 8. read csr 9. read fifo 10. clear rx_out if last packet, set data_end set force_stall 11. set uiar (ep0 inta) status stage with write data stage 1. [sync]-[in] 2. send data1(0) 3. if crc ok, send [sync]-[ack] 4. set tx_complete bit 5. interrupt 6. read uisr host usb macro microcontroller
26 5665b?usb?04/05 AT76C713 atmel confidential 6.7.10 interrupt and bulk in transfers the usb hardware automatically starts the endpoint in the receive mode and naks all in tokens, as long as the csr[tx packet ready] is cleared. the processor checks this bit and if it is 0, it writes the data into the fifo and then sets csr[tx packet ready]. at the next in token, the usb hardware sends the packet out and waits for an ack. until an ack is received, the usb hardware will retransmit the packet. after re ceiving an ack, the usb hardware clears the csr[tx packet ready], si gnaling a successful completion to the processor. figure 6-8. bulk in transfers 6.7.11 interrupt and bulk out transfers the usb hardware automatically starts the endp oint in receive mode. when an out token is received and if the csr[rx out packet] is cleared, it stores the data in the fifo. it acks the host if the data received are not corrupted and then interrupts the processor. if the csr[rx out packet] is set, the usb hardware responds with a nak to the incoming out token. the processor checks the csr[rx out packet] and if it is 1, it reads the data from the fifo and clears csr[rx out packet ready]. 7. read csr 8. clear tx_complete bit 9. clear data_end bit 10. set force_stall bit 11. set uiar (ep0 inta) host usb macro microcontroller in token without ping-pong in token with ping-pong in token host reads last data in token uc fills data tx_complete ack tx_pkt_rdy = 1 tx_complete = 1 ack tx_complete= 1 tx_pkt_rdy = 0 tx_pkt_rdy = 1 in token ack tx_complete= 1 tx_pkt_rdy = 0 tx_complete = 0 tx_complete =0 host reads last data in token uc fills data tx_complete ack tx_pkt_rdy = 1 tx_complete =1 tx_complete = 0 uc polling uc polling host reads usb fifo uc fills usb fifo host reads usb fifo
27 5665b?usb?04/05 AT76C713 atmel confidential figure 6-9. bulk out transfers 6.7.12 interrupt and isochronous transfers isochronous transfers use the same protocol with bulk transfers except that error correction and data packet retransmission are not supported: no ack token no nak token data pid is always 0 6.7.13 interrupt and interrupt in transfers interrupt transfers use the same protocol with bulk in transfers (interrupt out is not supported in usb spec 1.0). 6.7.14 suspend mode a usb device enters the suspend mode only when requested by the usb host through bus inactivity for at least 3 ms. the usb h/w detects this request, sets the susp bit of the sus- pend/resume register (sprsr), and interrupts t he processor if the interrupt is enabled. the processor should shut down any peripheral activity, enter power-down mode, and signal the usb h/w that it can enter the suspend mode by writing 1 to the sleep mode usb_macro input pin. the firmware must then execute the sleep in struction and set the system to a power-down state. the oscillator, pll, avr , and all peripherals will stop and the susp pin will be set to high.the usb suspend interrupt hits twice; one time in the beginning of the suspend, and one time at the end of the suspend. 6.7.15 resume mode resume mode is signaled by a j-to-k state transition at the usb port. the usb h/w enables the oscillator/pll and sets the rsm bit of the sprsr, which generates an interrupt. the pro- cessor starts executing where it left off and services the interrupt. the firmware clears the rcvd rsm bit. 6.7.16 remote wakeup during remote wakeup, a resume is signaled by the firmware by setting the rsm bit of the sprsr register.the firmware must wait for some time (8 ms) before clearing the the rsm bit in order to give time to the host to detect the resume signal on the bus. out token without ping-pong out token with ping-pong host fills usb fifo out token uc reads fifo rx_out =1 rx_out = 0 ack out token host fills usb fifo out token uc reads fifo rx_out =1 host fills usb fifo out token uc reads last data uc pooling rx_out rx_out =1 rx_out =0 ack host fills usb fifo out token uc reads last data uc pooling rx_out rx_out =1 rx_out =0 ack
28 5665b?usb?04/05 AT76C713 atmel confidential 6.8 uart0, uart1 uart0 and uart1 are 16550-compatible uarts with some additional features. the main features of the uarts are: can run 16550 software all registers are in 16550-compatible mode after reset programmable baud rate generator maximum data rate 921.6 kbaud exception handling using either prioritized interrupts or polled modes parity, framing, and overrun error detection two dedicated controller channels 16-byte transmit fifo 16-byte plus 3 error bits receive fifo 5-, 6-, 7-, and 8-bit word length bi-directional handshaking modem control signals (available only for uart0) line break generation and detection multidrop mode: address detection and generation diagnostic loopback mode (with or without an echo) 6.8.1 baud rate generator the input to the baud rate generator is 14.769 mhz, which is derived from the internal clock generator. 6.8.2 receiver the uart detects the start of a received word by sampling the sin signal until it detects a valid start bit. a low-level (that is, a spac e) on sin is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. thereore, a space which is longer than 7/16 of the bit period is det ected as a valid start bit. a space, which is 7/16 of a bit period or shorter, is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the sin at the theoretical midpoint of each bit. it is assumed that each bit lasts 16 cy cles of the sampling clock (1 bit period) so the sampling point is 8 cycles (0.5 bit periods) after the beginning of the bit. the first sampling point is sampled 24 cycles (1.5 bit periods) after the falling edge of the start bit was detected. each subsequent bit is sampled 16 cycles (1 bit period) after the previous one. 6.8.3 receive fifo operation the 16-byte plus 3 error bits receive data fifo is enabled by the fcr bit 0. the user can set the receiver trigger level. 6.8.4 time-out the receiver section includes a time-out mechanism in order to trace the time interval between the received words. the rto register contains the maximum bit peri ods, for which the uart will wait for the next word to arrive. whenever the time-out counter expires (reaches $00), then a time-out indication interrupt will be issued.
29 5665b?usb?04/05 AT76C713 atmel confidential the xr1[5] start time-out control bit selects the start time-out and rto load mechanism. if the xr1[5] bit is reset to 0 (16550 compatible mode), then the rto loads the value 4 times the word length plus 12 on each lcr write operation. after reset, the word length is 5 bits and the rto is $20. the time-out counter will then start counting down only in fifo mode (fcr[0] is set) and if the rx fifo holds at least 1 word. if xr1[5] is set to 1, then the time-out function is available and in fifo-disabled mode. the rto value does not change with the lcr write oper- ations. the time-out counter will st art counting down whenever the rto is not $00. in all cases, the core has immediate access to the contents of the rto. the time-out counter resets on a rhr read access from core or when a new word is completely received and transferred to the receive holding register or when the xr1[4] bit is forced to logic 1. 6.8.5 receive break the break condition is detected by the receiver when the sin line is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of all data, parity, and stop bits). at the moment of the low stop bit detection, the receiver asserts receive break indica- tion (lsr[4]). the end of the receive break is detect ed by a high level for at least 2/16 of the bit period. 6.8.6 transmitter the start bit, data bits, parity bit, and stop bits are serially shifted, with the lowest significant bit first, on the falling edge of the uart clock. the lcr controls the number of data bits, the parity bit and the number of stop bits. when a word is wr itten to thr (transmit holding register), it is transferred to the shift register as soon as it is empty. when the transfer occurs, the thr ready (bit-5) in lsr is set until a new word is written to thr. if the transmit shift register and thr are both empty, the transmitter empty (bit-6) in lsr is set. 6.8.7 transmit fifo operation when the fcr[0] is set to logic 1 and xr2[7] is reset to 0, then the 16-byte transmit fifo is enabled. the lcr[5] (and the xr2[5]) thr empty bit indicates whether the tx fifo is empty or full. when xr2[4] is in logic 0 (16550 compatible mode), then the thr empty bit indicates that tx fifo is empty. if xr2[4] is set to logic 1, then thr empty bit indicates tx fifo is not full. if the thr empty bit is active (high), th en a thr empty interrupt will be issued. the firmware has two choices: 1) reset xr2[4] bit to logic 0 and enable the thr empty inter- rupt. on each thr empty interrupt, the software will transfer up to 16 words to the thr (no check for fifo full). 2) set xr2[4] bit to logic 1 and enable thr empty interrupt. on each thr empty interrupt, the software will know that it is possible to transfer more words to thr (until thr empty bit is 0). 6.8.8 time-guard the time-guard function allows the transmitter to insert an idle state between two words on the sout line. the duration of the idle state is programmed in u _ttg (transmitter time-guard). when this register is set to 0, no time-guard is generated. 6.8.9 transmit break the transmitter can generate a break condition on the sout line when the start break com- mand is issued by setting lcr[6] to logic 1. during the break conditio n sout line is held to space state (logic 0). t he start break command will take effect right after the complete transmis- sion of all words in transmit shift register and thr (or tx fifo, if enabled). no software
30 5665b?usb?04/05 AT76C713 atmel confidential synchronization is needed. to remove the break condition on the sout line, a stop break com- mand should be issued by resetting us_lcr[6] to logic 0. the uart generates minimum break duration of one word length. after the stop break commandhas been issued, the sout line returns to high level (idle state) for at least 12 bit periods to ensure that the end of break is cor- rectly detected. the transmitter resumes the normal operation. 6.8.10 interrupt generation the uart prioritizes interrupts into five levels and records these in the interrupt identification register (iir). the five levels of interrupt conditions in order of priority are: receiver line status, rhr ready, time-out, thr ready, and modem status. when the cpu accesses the iir, the uart freezes the contents of iir and indicates t he highest priority pending an interrupt to the cpu. during this cpu access, th e uart records new interrupts, but does not change its current indication until the access is complete. the interrupt enab le register (ier) controls which interrupt co ndition will issue an interrupt to the core. disabling all interrupts, th e uart works in polled mode. 6.8.11 handshaking signals both uarts implement all the modem control handshaking signals, but none of those signals are mapped to any i/o port for uart1. for uart0, the nout1 and nout2 signals are not mapped to any i/o ports. the only available handshaking signals are the nrts, ncts, ndsr, ndtr, ncd, and nri of uart0. all modem control signals are bi-directional and the firmware has the full control of their status. 6.8.12 loopback mode in the diagnostic loopback mode, the uart deactiv ates the output signals (stack at logic 1) and loops-back their status to the proper input signal s. the uart offers the option of not stacking the uart output pins at logic 1 but rather echoing their status at the external uart interface. the loopback mode cannot be asserted if the direction of the modem control signals (mdr) are not in the default state. 6.9 irda 1.0 codec the irda 1.0 codec can be attached on either the uart0 or uart1. the operation of irda codec is controlled by the ?irda control register (irdacr)? on page 53 . the irda 1.0 codec can effect the uart?s sin and sout signals by applying 3/16 or 4/16 mod- ulation of the return-to-zero encoding scheme that the uart produces. according to the irda standard, for data rates up to and including 1.152 mbit/s, the rzi modula- tion scheme is used and a 0 is represented by a light pulse. for rates up to and including 115.2 kbit/s, the optical pulse duration is nominally 3/ 16 of a bit duration (or 3/16 of a 115.2 kbit/s bit duration). for 0.576 mbit/s and 1.152 mbit/s, the optical pulse duration is nominally 4/16 of a bit duration.
31 5665b?usb?04/05 AT76C713 atmel confidential figure 6-10. pulse duration 6.10 watchdog timer the main features of the watchdog timer (wdt) are: 3 mhz clock 22-bit up-counter programmable prescaler write access protection on the timer disable the wdt is used to prevent a system lock-up if the software becomes trapped in a deadlock. the wdt is clocked with a 3 mhz clock from the clock generator. in a normal operation, the user resets the wdt at regular inte rvals, using the wdr instructio n. by controlling the wdt pres- caler, the watchdog reset interval can be adjusted (see wdtcr register, wdp2..0 bits). eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the system resets and executes from the reset vector. to prevent unintentional disabling of the watchdog, a special turnoff sequence must be followed when the wdt is disabled. refer to the desc ription of the wdtcr register for details. 6.11 serial peripher al interface (spi) the AT76C713 spi features are: full-duplex 3-wire synchronous data transfers master or slave operation lsb first or msb first data transfer four programmable bit rates end-of-transmission interrupt request write collision flag protection wake-up from idle or power-down mode (slave mode only) the serial peripheral interface (spi) allows hi gh-speed synchronous data transfers between the AT76C713 and peripheral devices (memories, controllers, etc.). the interconnection between master and slave spi controllers is shown in figure 6-11 . the two shift registers of the master and the slav e spi controllers can be considered as one dis- tributed 16-bit circular shift register. as figure 6-11 shows, when data is shifted from the master nrz ? bit <115.2kbps 1.6 sec 0.576 and 1.152 mbps
32 5665b?usb?04/05 AT76C713 atmel confidential to the slave, data is also shifted in the opposi te direction simultaneously. this means that during one shift cycle the data in the master and the slave are interchanged. figure 6-11. interconnection between master and slave spi controllers the pb4(sck) pin is the clock output in the master mode and the clock input in the slave mode. writing to the spi data register of the spi master starts the spi clock generator and the data written shifts out of the master mosi pin and into the slave mosi pin. after shifting one byte, the spi clock generator stops setting the end-of-transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is issued. the slave select input (nss) is set low to select an individual slave spi device. the system is single-buffered in both transmit and receive directions. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is com- pleted. when receiving data, we must read t he received byte before the next reception is started. otherwise, the first byte is lost. when the spi is enabled (periphen register, spi bit), the data direction of the mosi, miso, sck, and nss pins is overridden, according to table 6-14 . 6.11.1 nss(pb4) pin functionality when the spi is configured as a master (mstr in spcr register), the user can determine the direction of the nss (pb4) pin. if the nss is configured as an output, the pin is a general output pin, which does not affect the spi system. if the nss is configured as an input, it must be held high to ensure master spi operation. if the nss pin is driven low by peripheral circuitry when the spi is configured as master with the nss pin defined as an input, then the spi system interprets this as another master selecting the spi as a slav e and starts to send data to it. to avoid bus contention, the spi system takes the following actions table 6-14. data direction of spi pins pin spi master spi slave description pb4 user defined input nss (spi slave select input) pb5 output input mosi (spi bus master output/slave input) pb6 input output/hi-z miso (spi bu s master input/slave output) pb7 output input sck (spi bus serial clock) spi master spi slave 8-bit shift register 8-bit shift register spi clock generator mosi mosi miso miso sck sck nss nss
33 5665b?usb?04/05 AT76C713 atmel confidential 1. the mstr bit in spcr is cleared and the spi system becomes a slave. as a result of the spi becoming a slave, the mosi and sck pins become inputs. 2. the spif flag in spsr is set, and if the spi interrupt is enabled and the i-bit in sreg is set, then the interrup t routine will be executed. thus, when the interrupt-driven spi transmittal is used in the master mode and there exists a possibility that the nss is driven low, the interrupt should alwa ys check that the mstr bit is still set. once the mstr bit has been cleared by a slave select, it must be set by the user to re- enable the spi master mode. when the spi is configured as a slave, the nss pin is always an input. when nss is held low, the spi is activated and miso becomes an output. all other pins (mosi and sck) are inputs. when nss is driven high, all pins are inputs and the spi is pass ive, which means that it will not receive incoming data. note that the spi logic w ill be reset once the nss pin is brought high. if the nss pin is brought high durin g a transmission, the spi will st op sending and receiving imme- diately, and both data received and data sent must be considered lost. 6.11.2 spi modes the spi bus protocol includes 4 modes. these modes determine the relationship between the serial clock and the data bits. the spi mode is fully programmable using the spi control register (spicr). the four modes are determined with the cpol and cpha bits, as illustrated in the fol- lowing four figures. note: in all modes, the data pins mosi and miso are driven in the opposite sclk edge. for example, if the data input is latched on the rising edge, then the data output is driven on the falling edge. figure 6-12. spi mode 0 figure 6-13. spi mode 1 mode 0: cpol= 0, cpha = 0 nss sck mosi/miso d6 d7 d5 d4 d3 d2 d1 d0 mode 1: cpol= 0, cpha =1 nss sck mosi/miso d6 d7 d5 d4 d3 d2 d1 d0
34 5665b?usb?04/05 AT76C713 atmel confidential figure 6-14. spi mode 2 figure 6-15. spi mode 3 6.12 jtag interface a nd on-chip debug system the main features of the jtag and on-chip debug (ocd) system are: jtag (ieee std. 1149.1 compliant) interface boundary-scan capabilitie s according to the i eee std. 1149.1 (jtag) debugger access to: ? all internal peripheral units ? internal and external data ram ? program memory ? internal register file ? program counter extensive on-chip debug support for break conditions, including: ? avr break instruction ? break on change of program memory flow ? single step break ? program memory break points on a single address or address range ? data memory break points on a single address or address range the avr ieee std. 1149.1 compliant jtag interface can be used for the following: testing pcbs by using the jtag boundary-scan capability on-chip debugging detailed descriptions for the bo undary-scan chain can be foun d in the section ?ieee 1149.1 (jtag) boundary-scan? of the i eee 1149.1 standar d. the on-chip debug support cont ains con- fidential jtag instructions and is distributed within atmel and to selected third party vendors only. mode 2: cpol=1, cpha = 0 nss sck mosi/miso d6 d7 d5 d4 d3 d2 d1 d0 mode 3: cpol=1, cpha =1 nss sck mosi/miso d6 d7 d5 d4 d3 d2 d1 d0
35 5665b?usb?04/05 AT76C713 atmel confidential figure 6-16 shows a block diagram of the jtag interface and the on-chip debug system. the tap controller selects either the jtag instruction register or one of several data registers as the scan chain (shift register) between the tdi input and tdo output. the instruction register holds jtag instructions controlling th e behavior of a data register. the id register, bypass register, and the boundary -scan chain are the data registers used for board-level testing. the internal scan-chain and break point scan chain are used for on-chip debugging purposes only. figure 6-16. jtag interface and on-chip debug system block diagram 6.12.1 test access port (tap) the jtag interface is accessed through four pi ns. in jtag terminology, these pins constitute the test access port (tap). these four pins are: tms: test mode select - this pin is used for navigating through the tap-controller state machine tck: test clock - jtag operation is synchronous to tck tdi: test data in - serial input data to be shifted in to the instruction register or data register (scan chains) tdo: test data out - serial output data from instruction register or data register the ieee std. 1149.1 also specifies the optional tap signal trst (test reset) which is not provided. for the on-chip debug system, in addition to the jtag interface pins, the nrst pin is monitored by the debugger in order to detect external re set sources. the debugger can also pull the nrst pin low (using the avr_reset command) in order to reset the entire system. 6.12.2 tap controller the tap controller is a 16-state finite-state machine that controls the operation of the boundary- scan circuitry or the on-chip debug system. the state transitions depicted in figure 6-17 depend tdi tdo tms tck tap controller m u x instruction register id register bypass register break point scan chain address decoder break point unit ocd status and control program memory controller flow control unit pc avr cpu jtag/avr core communication interface peripheral units boundary scan chain i/o pins internal scan chain instruction
36 5665b?usb?04/05 AT76C713 atmel confidential on the signal present on the tms (shown adjacent to each state transition) at the time of rising edge at the tck. the initial state after a power-on reset is a test-logic-reset. as a definition in this document, the lsb is shifted in and out first for all shift registers. assuming run-test/idle is the present state, a typi cal scenario for using the jtag interface is as follows: in the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of the tck to enter the shift instruction register (shift-ir) state. while in this state, shift the four bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of the instruction is shifted in when this state is left by setting the tms to high. while the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a particular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. at the tms input, apply the sequence 1, 0, 0 at the rising edges of the tck to enter the shift data register (shift-dr) state. while in this state, upload the selected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge of the tck. in order to remain in the shift-dr state, the tms input must be held low during the input of all bits except the msb. the msb of the data is shifted in when this state is left by setting the tms high. while the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states are only used for navigating the state machine. as shown in the state diagram, the run-test/idle state need not be entered between selecting jtag instruction and using the data registers. so me jtag instructions may select certain func- tions to be performed in the run-test/idle, making it unsuitable as an idle state. note: independent of the initial state of the tap co ntroller, the test-logic-reset state can always be entered by holding the tms high for five tck clock periods.
37 5665b?usb?04/05 AT76C713 atmel confidential figure 6-17. jtag tap state diagram 6.12.3 using the on-chip debug system as shown in figure 6-16 on page 35 , the hardware support for the on-chip debugging consists mainly of the following: a scan chain on the interface between the internal avr cpu and the internal peripheral units break point unit communication interface between the cpu and jtag system all read or modify/write operations needed for implementing the debugger are done by applying avr instructions via the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location which is part of the communication interface between the cpu and the jtag system. the break point unit implements a break on the change of program flow, single step break, two program memory break points, and two combined break points. together, the four break points can be configured as either: four single program memory break points three single program memory break point plus 1 single data memory break point two single program memory break points plus 2 single data memory break points two single program memory break points plus1 program memory break point with mask (?range break point?) two single program memory break points plus 1 data memory break point with mask (?range break point?) run-test/idle tms =0 tms = 1 tms =1 pause-ir tms = 0 tms = 0 tms =1 tms = 0 tms =1 tms =1 tms =1 tms = 0 tms = 0 tms = 0 tms =1 test-logic-reset tms=1 select-dr-scan tms =1 tms =1 select-ir-scan tms = 0 capture-dr capture-ir tms =1 tms = 0 tms = 0 shift-dr shift-ir tms =1 exit1-dr exit1-ir tms =1 tms = 0 tms = 0 pause-dr tms = 0 exit2-dr exit2-ir tms =1 update-dr update-ir tms = 0 tms = 0 tms =1 tms =1 tms = 0
38 5665b?usb?04/05 AT76C713 atmel confidential however, a debugger may use one or more of these resources for its internal purpose, leaving less flexibility to the end user. 6.12.4 on-chip debug specific jtag instructions the on-chip debug support contains private jtag instructions and distributed within atmel and to selected third party vendors only. instruction opcodes are listed for reference in the table 6- 15 . 6.13 i eee 1149.1 (jtag) boundary-scan features: jtag (ieee std. 1149.1 compliant) interface boundary-scan capabilities acco rding to the jtag standard full scan of all port functions, as well as analog circuitry having off-chip connections supports the optional idcode instruction additional public avr_reset instruction to reset the avr the boundary-scan chain has the c apability of driving an d observing the logic levels on the digi- tal i/o pins. at system level, all ics having jt ag capabilities are connected serilly by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins and observe the input values received from other devices. the con- troller compares the received data with the expected result. in this way, the boundary-scan provides a mechanism for testing interconnections and integrity of components on printed cir- cuits boards by using the four tap signals only. the four ieee 1149.1 defi ned mandatory jtag instruct ions idcode, bypass, sam- ple/preload, and extest, as well as the avr-specific public jtag instruction avr_reset can be used for testing the printed circuit board. initial scanning of the data regis- ter path will show the id code of the device, since idcode is the default jtag instruction. it may be desirable to have the avr device in reset during test mode. if not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an unde- termined state when exiting the test mode. enteri ng reset, the outputs of any port pin will instantly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the device. the device can be set in the reset state either by pulling the external nrst pin low, or issuing the avr_reset instructio n with appropriate setting of the reset data register. the extest instruction is used for sampling external pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir register. the sample/preload instruction should also be used for setting initial values to the scan ring in or der to avoid damaging the board when issuing the table 6-15. ocd specific jtag instructions opcode description private 0; $8 private jtag instruction for accessing on-chip debug system private 1; $9 private jtag instruction for accessing on-chip debug system private 2; $a private jtag instruction for accessing on-chip debug system private 3; $b private jtag instruction for accessing on-chip debug system
39 5665b?usb?04/05 AT76C713 atmel confidential extest instruction for the first time. the sam ple/preload instruction can also be used for taking a snapshot of the external pins during normal operation of the part. when using the jtag interface for the boundary-scan, using a jtag tck clock frequency higher than the internal chip frequency is po ssible. the chip clock is not required to run. 6.13.1 data registers the data registers relevant to the boundary-scan operations include: bypass register device identification register reset register boundary-scan chain 6.13.1.1 bypass register the bypass register consists of a single shift register stage. when the bypass register is selected as a path between the tdi and tdo, th e register is reset to 0 when leaving the cap- ture-dr controller state. the bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. 6.13.1.2 device identification register 6.13.1.3 reset register the reset register is a test data register used to reset the part. since the avr tri-states port pins when reset, the reset register can also replace the function of the not implemented optional jtag instruction highz. a high value in the reset regist er corresponds to pulling the exte rnal reset low. the part is reset, as long as there is a high value present in the reset register. the output from this data register is not latched, so the reset will take place immediately. 6.13.1.4 boundary-scan chain register the boundary-scan chain has the c apability of driving an d observing the logic levels on the digi- tal i/o pins. see the ?boundary-scan chain? on page 41 for a complete description. 6.13.2 boundary-scan specific jtag instructions the instruction register is 4-bit wide and suppor ts up to 16 instructions. listed below are the jtag instructions useful for the boundary-scan operation. note that the optional highz instruc- bit field value description 31:28 version $1 version is a 4-bit number identifying the revision of the component 27:12 part number $c712 the part number is a 16-bit code identifying the component. the unique jtag part number for AT76C713 and AT76C713 is $c712 11:1 manufacturer id $01f the manufacturer id is an 11-bit code identifying the manufacturer. the jtag manufacturer id for atmel is $01f 01 $1
40 5665b?usb?04/05 AT76C713 atmel confidential tion is not implemented, but all outputs with tri-state capabilit y can be set in a high-impedance state by using the avr_reset instruction, since the initial state for all port pins is tri-state. as a definition in this data sheet, the lsb is shifted in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in a hex format. the text describes which data register is selected as the path between the tdi and tdo for each instruction. 6.13.2.1 extest; $0 extest; $0 is the mandatory jtag instruction for selecting the boundary-scan chain as the data register for testing circuitry external to the avr package. the contents of the latched out- puts of the boundary-scan chain are driven out as soon as the jtag ir-register is loaded with the extest instruction. the active states are: capture-dr: data on the external pins is sampled into the boundary-scan chain shift-dr: the internal scan chain is shifted by the tck input update-dr: data from the scan chain is applied to output pins 6.13.2.2 idcode; $1 idcode; $1 is an optional jtag instruction selecting the 32 bit id-register as the data register. the id-register consists of a version number, a device number, and the manufacturer code cho- sen by jedec. this is the default instruction after power-up. the active states are: capture-dr: data in the idcode register is sampled into the boundary-scan chain shift-dr: the idcode scan chain is shifted by the tck input. 6.13.2.3 sample_preload; $2 sample_preload; $2 is a mandatory jtag instruction for pre-loading the output latches and taking a snap-shot of the input/ output pins without affecting th e system operation. however, the output latches are not connected to the pins. the boundary-scan chain is selected as data reg- ister. the active states are: capture-dr: data on the external pins are sampled into the boundary-scan chain. shift-dr: the boundary-scan chain is shifted by the tck input update-dr: data from the boundary-scan chain is applied to the output latches. however, the output latches are not connected to the pins 6.13.2.4 avr_reset; $c avr_reset; $ c is the avr-specific public jtag instruction for forcing the avr device into the reset mode or releasing the jtag reset source. the tap controller is not reset by this instruc- tion. the one bit reset register is selected as th e data register. note that the reset will be active as long as there is a logic 1 in the reset chain. the output from this chain is not latched. the active states are: shift-dr: the reset register is shifted by the tck input
41 5665b?usb?04/05 AT76C713 atmel confidential 6.13.2.5 bypass; $f bypass; $f is the mandatory jtag instruction selecting the bypass register for data register. the active states are: capture-dr: loads a logic 0 into the bypass register shift-dr: the bypass register cell between tdi and tdo is shifted 6.13.3 boundary-scan chain the boundary-scan chain consists of two kind of cells. the first one is a standard scan cell with observe and drive ca pabilities, while the second o ne is an observe-only cell. 6.13.3.1 AT76C713 boundary-scan order table 6-16 shows the scan order between the tdi and tdo when the boundary-scan chain is selected as the data path. bit 0 is the lsb; the first bit scanned in, and the first bit is scanned out. the scan order follows the pin-out order. therefore, the bits of port a for example are not scanned in order. figure 6-18 shows an i/o pin with scan logic. figure 6-18. i/o pin with scan logic table 6-16. AT76C713 boundary-scan order bit number signal name description (lsb) 0 test_en (observe only) 1 test_ck (observe only) 2 nrst (observe only) 3eout7 pe7 4ein7 5eoe7 6eout6 pe6 7ein6 8eoe6 9eout5 pe5 10 ein5 11 eoe5 enb pa d xoutn xinn oexn ddrdxn portxn pinxn note: x=a,b,c,d,e n=0..7 i/o registers boundary scan signals scan cell scan cell scan cel
42 5665b?usb?04/05 AT76C713 atmel confidential 12 eout4 pe4 13 ein4 14 eoe4 15 eout3 pe3 16 ein3 17 eoe3 18 eout2 pe2 19 ein2 20 eoe2 21 eout1 pe1 22 ein1 23 eoe1 24 eout0 pe0 25 ein0 26 eoe0 27 pmode0 28 pmode1 29 cout7 pc7 30 cin7 31 coe7 32 cout6 pc6 33 cin6 34 coe6 35 cout5 pc5 36 cin5 37 coe5 38 cout4 pc4 39 cin4 40 coe4 41 cout3 pc3 42 cin3 43 coe3 44 cout2 pc2 45 cin2 46 coe2 table 6-16. AT76C713 boundary-scan order (continued) bit number signal name description
43 5665b?usb?04/05 AT76C713 atmel confidential 47 cout1 pc1 48 cin1 49 coe1 50 cout0 pc0 51 cin0 52 coe0 53 bout7 pb7 54 bin7 55 boe7 56 bout6 pb6 57 bin6 58 boe6 59 bout5 pb5 60 bin5 61 boe5 62 bout4 pb4 63 bin4 64 boe4 65 bout3 pb3 66 bin3 67 boe3 68 bout2 pb2 69 bin2 70 boe2 71 dout7 pd7 72 din7 73 doe7 74 dout6 pd6 75 din6 76 doe6 77 dout5 pd5 78 din5 79 doe5 80 dout4 pd4 81 din4 82 doe4 table 6-16. AT76C713 boundary-scan order (continued) bit number signal name description
44 5665b?usb?04/05 AT76C713 atmel confidential 83 dout3 pd3 84 din3 85 doe3 86 dout2 pd2 87 din2 88 doe2 89 dout1 pd1 90 din1 91 doe1 92 dout0 pd0 93 din0 94 doe0 95 suspend 96 aout7 pa 7 97 ain7 98 aoe7 99 aout6 pa 6 100 ain6 101 aoe6 102 aout5 pa 5 103 ain5 104 aoe5 105 aout4 pa 4 106 ain4 107 aoe4 108 aout3 pa 3 109 ain3 110 aoe3 111 usb_attach 112 ncs1 113 ncs0 114 nfwr 115 nfrd 116 aout2 pa 2 117 ain2 118 aoe2 table 6-16. AT76C713 boundary-scan order (continued) bit number signal name description
45 5665b?usb?04/05 AT76C713 atmel confidential 7. i/o space (register description) the i/o space definition of the AT76C713 is shown in table 7-1 . this space is defined in the area $00 - $3f and can be directly accessed by in and out instructions or by ordinary sram accesses in the area $ 20-$5f. the notation us ed (with the sram addre ss in parentheses), will be followed in the rest of this document. 119 aout1 pa 1 120 ain1 121 aoe1 122 aout0 pa 0 123 ain0 124 aoe0 125 bout1 pb1 126 bin1 127 boe1 128 bout0 pb0 129 bin0 130 boe0 131 idle-mode (sleep state) (observe only) 132 power-down (sleep state) (observe only) 133 avr clock stopped (observe only) 134 pll stable indication (observe only) (msb) 135 pll lock signal (observe only) table 6-16. AT76C713 boundary-scan order (continued) bit number signal name description table 7-1. AT76C713 i/o space i/o address (sram address) name function $3f($5f) sreg status register $3e($5e) sph stack pointer high $3d($5d) spl stack pointer low $3c($5c) idr ocd debug register $39($59) timsk timer interrupt mask register $38($58) tifr timer interrupt flag register $37($57) eimsk external interrupt mask register $35($55) mcucr mcu general control register $34($54) mcusr mcu status register $33($53) tccr0 timer0 control registerregister
46 5665b?usb?04/05 AT76C713 atmel confidential $32($52) tcnt0 timer0 (8-bit) $31($51) preld0 pre-load register 0 $2e($4e) tccr1b timer1 control register b $2d($4d) tcnt1h timer1 high byte $2c($4c) tcnt1l timer1 low byte $2b($4b) ocr1ah timer1 output compare register a high byte $2a($4a) ocr1al timer1 output compare register a low byte $29($49) ocr1bh timer1 output compare register b high byte $28($48) ocr1bl timer1 output compare register b low byte $27($47) icr1h timer1 input capture register high byte $26($46) icr1l timer1 input capture registerregister low byte $25($45) tccr2 timer2 control register $24($44) tcnt2 timer2 (8-bit) $23($43) preld2 pre-load register 2 $22($42) irdacr irda control register $21($41) wdtcr watchdog timer control register $1f($3f) pmod program mode (pmo de0, pmode1 pins value) $1d($3d) emicrb external memory interf. control registerb $1c($3c) emicra external memory interf. control register a $1b($3b) porta data register, port a $1a($3a) ddra data direction register, port a $19($39) pina input pins, port a $18($38) portb data register, port b $17($37) ddrb data direction register, port b $16($36) pinb input pins, port b $15($35) portc data register, port c $14($34) ddrc data direction register, port c $13($33) pinc input pins, port c $12($32) portd data register, port d $11($31) ddrd data direction register, port d $10($30) pind input pins, port d $0f($2f) spdr spi i/o data register $0e($2e) spsr spi status register $0d($2f) spcr spi control register $0c($2c) clk_cntr clock control register table 7-1. AT76C713 i/o space (continued) i/o address (sram address) name function
47 5665b?usb?04/05 AT76C713 atmel confidential avr status register (sreg) addr $3f($5f) 8 bits stack pointer (sp) addr $3e($5e), $3d($5d) 11 bits $0b($2b) periphen peripheral enable register $0a($2a) porte data register, port e $09($29) ddre data direction register, port e $08($28) pine input pins, port e bit field avr description 7 i:global interrupt enable r/w when set, the interrupts are enabled. the individual interrupt enable control is performed in the individual mask registers. this bit is cleared by h/w after an interrupt has occurred and is set by the reti instruction to ena ble subsequent interrupts 6 t: bit copy storage r/w bit load (bld) and bit store (bst) instructions use the t bit as source and destination for the operated bit 5 h: half carry flag r/w indicates a half carry in some arithmetic operations 4 s: sign bit r/w is an exclusive or between the negative flag n and the two?s complement overflow flag v 3 v: two?s complement overflow flag r/w supports two?s complement arithmetic 2 n: negative flag r/w when set, this indicates a negative result in arithmetic and logic operations 1 z: zero flag r/w when set, this indicates a 0 result after the different arithmetic and logic operations 0 c: carry flag r/w when set, this indicates a carry in the arithmetic or logic operations bit field avr description 15:11 - r/w sph 10 sp10 r/w 9 sp9 r/w 8 sp8 r/w table 7-1. AT76C713 i/o space (continued) i/o address (sram address) name function
48 5665b?usb?04/05 AT76C713 atmel confidential external memory interface control register a (emicra) addr $1c($3c) 8 bits external memory interface control register b (emicrb) addr $1d ($3d) 8 bits 7 sp7 r/w spl 6 sp6 r/w 5 sp5 r/w 4 sp4 r/w 3 sp3 r/w 2 sp2 r/w 1 sp1 r/w 0 sp0 r/w bit field default avr description 7rw1 0 r/w these bits control the wait states inserted in the corresponding (read, write and ale) signals 6rw0 0 r/w 5rm1 0 r/w these bits control the mode (waveform) of the corresponding (read, write and ale) signals 4rm0 0 r/w 3ww1 0 r/w these bits control the wait states inserted in the corresponding (read, write and ale) signals 2ww0 0 r/w 1wm1 0 r/w these bits control the mode (waveform) of the corresponding (read, write and ale) signals 0wm0 0 r/w bit field default avr description 7aw1 0 r/w these bits control the wait states inserted in the corresponding (read, write and ale) signals 6aw0 0 r/w 5am1 0 r/w thse bits control the mode (waveform) of the corresponding (read, write and ale) signals 4am0 0 r/w bit field avr description
49 5665b?usb?04/05 AT76C713 atmel confidential mcu control re gister (mcucr) the mcu control register controls the ef fect of the sleep instructio n (see avr instruction set). note that when the avr is in sl eep mode (st and-by or power-down mode), it will wake up on any enabled interrupt or on any usb activity (if the u sb core is activated). also, on any jtag activ- ity, if the system is in the power-down mode, it switches into stand-by mode. addr $35 ($55) 8 bits 3:2 ? 0 r/w 1 emd0 0 r/w these bits select the external memory interface mode according to the following table 0emd1 0 r/w bit field default avr description 7? 0 ? reserved 6 se:slee p enable 0r/w when set, this permits the mcu to enter in the sleep mode when the sleep instruction is executed 5 sm:sle ep mode select bit 0r/w this bit selects between the two available sleep modes when the mcu enters into the sleep state and the sm bit is cleared, then it enters into idle mode and only the avr clock is stopped. otherwise, if the sm bit is set, then the mcu enters into the power- down mode and the mcu disables the oscillator, stopping all clocks and any activity 4:0 ? 0 ? reserved bit field default avr description emd1 emd0 external memory interface mode 0 0 fifo 01 reserved 1 0 demultiplexed 1 1 multiplexed
50 5665b?usb?04/05 AT76C713 atmel confidential mcu status register (mcusr) the mcu status register provides information on which reset source caused an mcu reset. addr $34 ($54) 8 bits the user program must clear these bits as early as po ssible. if these bits are cleared before a reset condi- tion occurs, the source of resource can be found by using the truth table shown in table 7-3 . external interrupt mask register (eimsk) the external interrupt mask register masks the external interrupts. external interrupts should be acknowledged using general-purpose output pins. addr $37 ($57) 8 bits bit field default avr description 7:2 ? ? ? ? 1 extrf: externa l reset flag see table 7- 2 r/w external reset flag. this flag indicates that an external reset has occurred 0 porf: power on reset flag r/w this flag indicates that a power-on reset has occurred table 7-2. porf and extrf values after reset reset source porf extrf power-on reset 1 undefined external reset unchanged 1 watchdog reset unchanged unchanged table 7-3. reset source identification porf extrf reset source 0 0 watchdog reset 0 1 external reset 1 x power on reset bit field default avr description 7 pol3: polarity of external interrupt 1 0 r/w int3 is active high when this bit is low 6 pol2: polarity of external interrupt 1 0 r/w int2 is active high when this bit is low 5 pol1: polarity of external interrupt 1 0 r/w int1 is active high when this bit is low
51 5665b?usb?04/05 AT76C713 atmel confidential clock control regi ster (clk_cntr) the clock control register controls the clock generation circuit. for example, the pll output clock rate can be switched from 96 mhz to 192 mhz by setting the clk_cntr register to $4c. addr $0c ($2c) 8 bits 4 pol0: polarity of external interrupt 0 0 r/w int0 is active high when this bit is low 3int3 0r/w if this is set and the i-bit in the status register is set, the external pin interrupt 3 is enabled 2int2 0r/w if this is set and the i-bit in the status register is set, the external pin interrupt 2 is enabled 1int1 0r/w if this is set and the i-bit in the status register is set, the external pin interrupt 1 is enabled 0int0 0r/w if this is set and the i-bit in the status register is set, the external pin interrupt 0 is enabled bit field default avr description 7npicp 0 r/w is equal to the reversed pll icp bit. controls the pll charge-pump current 6 plck 0 r/w if this is set, the pll lock signal is used for ?pll stable? indication. if cleared, the ?pll stable? indication is equal to the ?pll enable? signal delayed by a significant factor 5 udpll 0 r/w select dpll96 instead of dpll48 for usb clock recovery 4 osc_nslp 0 r/w if this is set, then do not close the oscillator during the power-down sleep mode 3pivco1 0 r/w pll ivco[1]. selects the pll frequency range. normally, this bit must be equal to the mul16 bit 2mul16 0 r/w selects the multiplier of the pll. when this is set, the external 12 mhz crystal frequency is multiplied by 16 to generate an internal fast clock of 192 mhz. when cleared, the external 12 mhz crystal frequency is multiplied by 8, generating an internal fast clock of 96 mhz 1 mcsp1 0 r/w avr core speed select bits. these bits control the avr clock divisor according to table 7-4 0 mcsp0 0 r/w table 7-4. microcontroller speed select bits mul16 mcsp1 mcsp0 avr clock rate notes 0 0 0 24 mhz 96 div 4 0 0 1 19, 2 mhz 96 div 5 0 1 0 16 mhz 96 div 6 011 reserved 1 0 0 48 mhz 192 div 4 bit field default avr description
52 5665b?usb?04/05 AT76C713 atmel confidential peripheral enable control register (periphen) the peripheral enable control register enables the peripheral components of the system. it con- trols the spi, uarts, usb, and external memory controllers. addr $0b ($2b) 8 bits program mode register (pmod) the program mode register returns the value of the pmode0 and pmode1 input pins. addr $1f ($3f) 8 bits 1 0 1 38,4 mhz 192 div 5 1 1 0 32 mhz 192 div 6 111 reserved bit field default avr description 7:6 ? 0 r this bit is always read as 0 5 spi: spi enable 0 r/w when set, this bit enables the spi controller 4 uart1 enable 0 r/w when set, this bit enables the function of uart1 3 uart0 enable 0 r/w when set, this bit enables the function of uart0 2 uattach 0 r/w when set, this bit activates (logic 1) the usb_attach pin 1usb enable 0 r/w when set, this bit enables the function of usb (clock enable) 0 emien: external memory interface enable 0r/w when set, this bit enables the external memory interface and the pin functions of port a and port c (1) are set to their alternative pin functions. the emen bit overrides any bit direction settings in the respective data direction registers bit field default avr description 7:2 ? 0 r always read as 0 1 pmode1 n/a r the value of the pmode1 input pin 0 pmode0 n/a r the value of the pmode0 input pin table 7-4. microcontroller speed select bits mul16 mcsp1 mcsp0 avr clock rate notes
53 5665b?usb?04/05 AT76C713 atmel confidential i/o debug register (idr) the i/o debugs register communicates between the on-chip debug system (through jtag) and the avr cpu. it provides a communication channel from the running program in the microcon- troller to the debugger. the cpu can transfer a byte to the debugger by writing to this location. addr $3c ($5c) 8 bits irda control register (irdacr) the irda control register controls the irda 1.0 codec. the irda codec is connected between the uart0 and uart1 sin and sout signals and the corresponding pins. addr $22 ($42) 8 bits bit field default avr description 7 idrd:i/o debug register dirty 0r/w this bit is set to indicate to the debugger that the register has been written 6 0r/w when the cpu reads the idr register, the 7 lsb will be from the idr register, while th e msb is from the idrd bit. the debugger clears the idrd bit after it has read the information 5 0r/w 4 0r/w 3 0r/w 2 0r/w 1 0r/w 0lsb 0r/w bit field default avr description 7:5 ? 0 r 4 txpol: transmit polarity 0 r/w if this bit is set, the sout signal is inverted 3 rxpol: receive polarity 0r/w if this bit is set, the sin signal is inverted before entering the irda codec 2mode 0r/w when this bit is cleared, it enables the 3/16 return-to-zero encoding scheme. when this bit is set, it enables the 4/16 return-to-zero encoding scheme 1 usel: uart select 0r/w when this bit is cleared, the codec uses uart0. when this bit is set, the codec uses uart1 0 irdaen 0 r/w when this bit is set, it enables the irda codec. when this bit is cleared, the codec is transparent to the uart0/1 sin/sout pins
54 5665b?usb?04/05 AT76C713 atmel confidential 7.1 timers/counters timer/counter interrupt mask register (timsk) the timer/counter interrupt mask register masks the internal timer interrupts. addr $39 ($59) 8 bits bit field default avr description 7 toie1: timer/counter 1 overflow interrupt enable 0r/w when this bit is set and the i-bit in the status register is 1, the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $001c) is executed if an overflow in timer/counter1 occurs. the timer/counter1 overflow flag is set in the timer/counter1 interrupt flag register (tifr) 6 ocie1a: timer/counter 1 output compare a match interrupt enable 0r/w when this bit is set and the i-bit in the status register is 1, the timer/counter1 compare a match interrupt is enabled. the corresponding interrupt (at vector $0018) is executed if a compare a match in timer/counter1 occurs. the compare a flag in timer/counter 1 is set, in the timer/counter interrupt flag register (tifr) 5 ocie1b: timer/counter 1 output compare b match interrupt enable 0r/w when this bit is set and the i-bit in the status register is 1, the timer/counter1 compare b match interrupt is enabled. the corresponding interrupt (at vector $001a) is executed if a compare b match in timer/counter1 occurs.the compare b flag in timer/counter 1 is set, in the timer/counter interrupt flag register (tifr) 4? 0r 3 ticie1: timer/counter 1 input capture interrupt enable 0r/w when this bit is set and the i-bit in the status register is 1, the input capture event in terrupt is enabled. the corresponding interrupt (at vector $0016) is executed if a capture event occurs on pin pb3. the input capture flag in timer/counter1 is set in the timer/counter interrupt flag register (tifr) 2 toie2: timer/counter 2 overflow interrupt enable 0r/w when this bit is set and the i-bit in the status register is 1, the timer/counter2 overflow interrupt is enabled. the corresponding interrupt (at vector $0020) is executed if an overflow in timer/counter2 occurs. the timer/counter2 overflow flag is set in the timer/counter2 interrupt flag register (tifr) 1 toie0: timer/counter 0 overflow interrupt enable 0r/w when this bit is set and the i-bi t in the status register is 1, the timer/counter0 overflow interrupt is enabled. the corresponding interrupt (at vector $0020) is executed if an overflow in timer/counter0 occurs. the timer/counter0 overflow flag is set in the timer/counter0 interrupt flag register (tifr) 0? 0r
55 5665b?usb?04/05 AT76C713 atmel confidential timer/counter interrupt flag register (tifr) addr $38 ($58) 8 bits 7.2 timer/counter 0 an d timer/counter 2 timer/counter 0 control register (tccr0) addr $33 ($53) 8 bits bit field default avr description 70r/w 6 ocfa: output compare flag a 0r/w the ocfa is set when a compare match between timer/counter1 and the ocr1a register occurs. this flag is cleared when written with a logic 1 5 ocfb: output compare flag 1b 0r/w the ocf1b is set when a compare match between timer/counter1 and the ocr1b register occurs. this flag is cleared when written with a logic 1 4? 0r 3 icf1: input capture flag 0r/w this flag when set indicates an input capture event, where the contents of the timer/counter1 are transferred to the icr1 register. this flag is cleared when written with a logic 1 2 tov2: timer/counter 2 overflow flag 0r/w timer/counter2 overflow flag. the tov2 is set when an overflow occurs in timer/counter2. this flag is cleared when written with a logic 1 1 tov0: timer/counter 1 overflow flag. 0r/w timer/counter0 overflow flag. the tov0 is set when an overflow occurs in timer/counter0. this flag is cleared when written with a logic 1 0? 0r bit field default avr description 7:3 ? 0 r
56 5665b?usb?04/05 AT76C713 atmel confidential the timer/counter2 control register (tccr2) addr $25 ($45) 8 bits 2cs02 0r/w 1cs01 r/w 0cs00 r bit field default avr description 7:3 reserved 0 r ? 2 cs02: clock select 0 bit 2 0r/w the clock select0 bits 2,1, and 0 define the pre-scaling source of timer0 1 cs01: clock select 0 bit 1 0r/w 0 cs00: clock select 0 bit 0 0r/w bit field default avr description cs02 cs01 cs00 description 000 stop, timer/counter0 is stopped 001ck 010ck/8 011ck/64 100ck/256 1 0 1 ck/1024 110 external pin t0 (ort2), falling edge 111 external pin t0 (or t2), rising edge cs02 cs01 cs00 description 000 stop, timer/counter0 is stopped 001ck 010ck/8 011ck/64 100ck/256 101ck/1024 110 external pin t0 (or t2), falling edge 111 external pin t0 (or t2), rising edge
57 5665b?usb?04/05 AT76C713 atmel confidential timer/counter0 register (tcnt0) addr $32 ($52) 8 bits timer/counter2 register (tcnt2) both timer/counter0 and timer/counter2 are realized as an up-counter with read and write access. if the tcnt0 (or tcnt2 respectively) is written and a clock source is present, the timer/counter0 (or timer/counter2) continues c ounting in the clock cycle following the write operation. addr $24 ($44) 8 bits bit field default avr description 7msb 0r/w both timer/counter0 and timer/counter2 are realized as an up-counter with read and write access. if the tcnt0 (or tcnt2 respectively) is written and a clock source is present, the timer/count er0 (or timer/counter2) continues counting in the clock cycle following the write operation 60r/w 50r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w bit field default avr description 7msb 0r/w both timer/counter0 and timer/counter2 are realized as an up-counter with read and write access. if the tcnt0 (or tcnt2 respectively) is written and a clock source is present, the timer/count er0 (or timer/counter2) continues counting in the clock cycle following the write operation 60r/w 50r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w
58 5665b?usb?04/05 AT76C713 atmel confidential pre-load register 0 (preld0) addr $31 ($51) 8 bits pre-load register 2 (preld2) addr $23 ($43) 8 bits bit field default avr description 7msb 0r/w an 8-bit r/w register with a 0 initial value. the contents of this register are loaded to timer/counter0 tcnt0 (or timer/counter2 tcnt2 respectively) after an overflow 60r/w 50r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w bit field default avr description 7msb 0r/w an 8-bit r/w register with 0 in itial value. the contents of this register are loaded to timer/counter0 tcnt0 (or timer/counter2 tcnt2 respectively) after an overflow 60r/w 50r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w
59 5665b?usb?04/05 AT76C713 atmel confidential 7.3 timer/counter 1 timer/counter1 register (tccr1b) addr $2e ($4e) 8 bits bit field default avr description 7 icnc1: input capture 1 noise canceler (4 cks 0r/w when this bit is 0, the input canceler function is disabled. the input capture is triggered at the first rising/falling edge sampled on the input capture pi n (icp), as specified by the ices1 bit. when this bit is set, four successive samples are measured and all samples must be high/low according to the input capture trigger specification in the ices1 bit. the actual sampling frequency is the cpu clock frequency 6 ices1: input capture1 edge select 0r/w when this bit is cleared, the timer/counter1 contents are transferred to the input capture register (icr1) on the falling edge of the icp. when th is bit is 1, the contents are transferred on the rising edge 5:4 ? 0 r 3 ctca1: clear timer/counter 1 on compare a match 0r/w when this bit is 1, the timer/counter1 is reset to $0000 after compare a match. if this bit is cleared, the timer/counter1 continues counting after a compare a match 2 cs12: clock select 1,bit 2 0r/w these bits select prescaling source for the timer/counter,1 according to the following table 1 cs11:clock select 1, bit 1 0r/w 0 cs11:clock select 0, bit 0 0r/w cs02 cs01 cs00 description 000 stop, timer/counter0 is stopped 001ck 010ck/8 011ck/64 100ck/256 1 0 1 ck/1024 110 external pin t0 (ort2), falling edge 111 external pin t0 (or t2), rising edge
60 5665b?usb?04/05 AT76C713 atmel confidential timer/counter1 (tcnt1h and tcnt1l) the timer/counter1 is realized as a 16-bit up coun ter consisted of two 8-bit registers tcnt1h and tcnt1l. these registers have read and write access with an initial value of $00. if the timer/counter1 (tcnt1h and tcnt1l) register is written to and a clock source is selected, the timer/counter1 continues counting in the timer clo ck cycle after it is preset with the written value. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary register (temp). this temporary register is also used when accessing ocr1a, ocr1b, and icr1. if the main program and also interrupt routines perform access to registers using temp, the interrupts must be disabled during access from the main program. addr $2d ($4d), $2c ($4c) 16 bits bit field default avr description 15 msb 0 r/w tcnt1 timer/counter1 write : when the cpu writes to the high byte tcnt1h, the written data is placed in the temp register. next, when the cpu writes the low byte tcnt 1l, this byte of data is combined with the temp regi ster and all 16-bits are written simultaneously to the timer/counter1 tcnt1 register. consequently, the high byte must be accessed first for a full 16-bit write operation. when using the timer/counter1 as an 8-bit counter, it is sufficient to write the low byte only tcnt1 timer/counter1 read : when the cpu reads the low byte tcnt1l, the data are placed in the temp register. next, when the cpu reads the high byte tcnt1h, the cp u receives the data in the temp register. consequently, the low byte must be accessed first for a full 16-bit read operation. when using timer/counter1 as an 8-bit counter, it is sufficient to read the low byte only 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 90r/w 80r/w 70r/w 60r/w 50r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w
61 5665b?usb?04/05 AT76C713 atmel confidential timer/counter1 output compare register a (ocr1ah and ocr1al) timer/counter output compare register a consists of 16 bits and is made by two 8-bit r/w reg- isters, with the initial value of 0, namely the ocr1ah and ocr1al. full 16-bit write and read operations are made according to the way specified for the timer/counter1 tcnt1. addr $2b ($4b), $2a ($4a) 16 bits timer/counter1 output compare register b (ocr1bh and ocr1bl) timer/counter output compare register b consists of 16 bits and is made by two 8-bit r/w reg- isters, with the initial value of 0, namely the ocr1bh and ocr1bl. full 16-bit write and read operations are made according to the way specified for the timer/counter1 tcnt1. addr $29 ($49), $28 ($48) 16 bits the timer/counter1 input capture register (icr1h and icr1l) the timer/counter input compare register consists of 16-bits and is made by two 8-bit read only registers, with initial value of 0, namely the icr1h and icr1l. when the rising or falling edge (according to the inpu t capture edge setting (ices1) of the sig- nal at the input capture pin (icp) is detected, the current value of the timer/counter1 is transferred to the input capture register (icr1). at the same time, the input capture flag (icf1) is set to 1. full 16-bit read operations are made according to the way specified for the timer/counter1 tcnt1 above. addr $27 ($47), $26 ($46) 16 bits bit field default avr description 15 msb 0 r/w ocr1ah 14:8 0 r/w 7:1 0 r/w ocr1al 0lsb 0r/w bit field default avr description 15 msb 0 r/w ocr1bh 14:8 0 r/w 7:1 0 r/w ocr1bl 0lsb0r/w bit field default avr description 15 msb 0 r ocr1h 14:8 0 r 7:1 0 r ocr1l 0lsb 0r
62 5665b?usb?04/05 AT76C713 atmel confidential 7.4 watchdog timer watchdog timer control register (wdtcr) addr $21 ($41) 8 bits bit field default avr description 7:5 ? 0 r 4 wdtoe: watchdog turn off enable 0r/w this bit must be set when the wde bit is cleared. otherwise, the watchdog timer will not be disabled. once set, h/w will clear this bit to 0 after four clock cycles 3 wde: watchdog enable 0r/w when this bit is set, the watchdog timer is enabled. when this bit is 0, the watchdog timer is disabled. the wde bit can only be cleared if the wdtoe bit is set. to disable an enabled watchdog timer, the following procedure must be followed: in the same operation, write a logical 1 to bits wdtoe and wde. a logical 1 must be written to the wde bit even though it is set to 1 before the disable operation starts. within the next four clock cycl es, write a logical 0 to bit wde. this disables the watchdog. 2 wdp2: watchdog timer prescaler 2 0r/w these bits determine the watchdog timer prescaling when the watchdog timer is enabled, according to table 7-5 1 wdp1:watc hdog timer prescaler 1 r/w 0 wdp0:watc hdog timer 0 prescaler 0 r/w table 7-5. watchdog timer prescale register select wdp2 wdp1 wdp0 time-out period 0 0 0 5.5 ms 16k cycles 0 0 1 11 ms 32k cycles 0 1 0 22 ms 64k cycles 0 1 1 47 ms 128k cycles 1 0 0 87 ms 256k cycles 1 0 1 175 ms 512k cycles 1 1 0 350 ms 1024k cycles 1 1 1 700 ms 2084k cycles
63 5665b?usb?04/05 AT76C713 atmel confidential 7.5 spi interface spi control register (spcr) addr $0d ($2f) 8 bits bit field default avr description 7 spie: spi interrupt enable 0r/w this bit causes the setting of the spif bit in the spsr register to execute the spi interrupt provided that the global interrupt is enabled 6 spe: spi enable 0r/w when this bit is set, the spi is enabled and ss, mosi, miso, and sck are connected to pins pb4, pb5, pb6, and pb7 5 dord: data order 0r/w when this bit is 1, the lsb of the data word is transmitted first. when this bit is cleared, the msb of the data word is transmitted first 4 mstr: master/slave select 0r/w this bit selects the master spi when set and the slave spi mode when cleared. if the ss is configured as input and driven low while the mstr is set, the mstr will be cleared, and the spif in the spsr will become set. the user will then have to set the mstr to re-enable the spi master mode 3 cpol: clock polarity 0r/w when this bit is set, sck is high when idle. when the cpol is cleared, the sck is low when idle 2 cpha: clock phase 0r/w when this bit is set, the data is valid in the falling edge of the sck if the cpol = 0, or in the rising edge of the sck when the cpol = 1. when this bis is cleared, the data is valid in the rising edge of the sck if the cpol = 0 and in the falling edge of the sck if the cpol = 1 1 spr1: spi clock rate select 1 0r/w these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect during the slave mode. the relationship between the slave and the avr clock frequency is shown in the following table: 0 spr0: spi clock rate select 0 0r/w spr1 spr0 scg frequency 0 0 {avr clock rate} div 4 0 1 {avr clock rate} div 16 1 0 {avr clock rate} div 64 1 1 {avr clock rate} div 128
64 5665b?usb?04/05 AT76C713 atmel confidential spi status register (spsr) addr $0e ($2e) 8 bits spi data register (spdr0 addr $0f ($2f) 8 bits 7.6 i/o ports 7.6.1 port a port a is an 8-bit bi-directional i/o port with internal pull-up resistors. 7.6.1.1 port a alternative functionality port a, besides its use as a general-purpose i/o port, is used to support alternate functions. specifically, serves also as the address and data bus of the external memory interface ad[0-7]. 7.6.1.2 port a i/o registers port a data register (porta) addr $1b ($3b) 8 bits bit field default avr description 7 spif: spi interrupt flag 0r/w when a serial transfer is complete, the spif bit is set and an interrupt is generated if spie in spcr is set and the global interrupts are enabled. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register. 6 wcol: write collision flag 0r/w the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol and the spif bits are cleared by first reading the spi status register with the wcol set, and then by accessing the spi data register 5:0 ? 0 r always read as 0 bit field default avr description 7msb 0r/w it is used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the r egister causes the shift register receive buffer to be read 6:1 0 r/w 0lsb 0r/w bit field default avr description 7 msb 0 r/w it is an 8-bit r/w register with zero initial value 0xff. the bits in the data direction regi ster control the direction of the corresponding pin in the port a. when bit ddrbx is set, then pbx pin is input, while when ddrbx is cleared pbx is output, x=0?7 6:1 0 r/w 0lsb 0r/w
65 5665b?usb?04/05 AT76C713 atmel confidential port a data direction register (ddra) addr $1a($3a) 8 bits port a input pins address (pina) addr $19($39) 8 bits 7.6.2 port b port b is an 8-bit bi-directional i/o port with internal pull-up resistors. 7.6.2.1 port b alternative functionality port b, besides its use as a general-purpose i/o port, is used to support alternate functions. specifically, the spi interface, the input capture pin for timer/counter1, and the external clocks for the timers/counters are implemented through the b port. when the spi is enabled, the data direction of port b pins 4..7 is overridden, according to table 7-6 . bit field default avr description 7msb 0r/w the bits in the data direction register control the direction of the corresponding pin in the port a. when bit ddrax is set ,then the pax pin is output, while when ddrax is cleared, the pax pin is input (x = 0..7) 60r/w 50r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w bit field default avr description 7msb n/ar the port a input pins address (pina) is not a physical register. this address enab les access to the physical voltage value on each port pin. it is a read-only address. the initial value of pina depends from status of each port a pin 6n/ar 5n/ar 4n/ar 3n/ar 2n/ar 1n/ar 0lsb n/ar table 7-6. port b pins alternate functions port pin direction alternate function pb0 (ddrb) external clock pin for timer/counter0 pb1 (ddrb) external clock pin for timer/counter1 pb2 (ddrb) input capture pin for timer/counter1 pb3 (ddrb) icp: capture for timer/counter 1 spi master spi slave
66 5665b?usb?04/05 AT76C713 atmel confidential 7.6.2.2 port b i/o registers port b data register (portb) addr $18 ($38) 8 bits port b data direction register (ddrb) addr $17 ($37) 8 bits pb4 (ddrb) input nss (spi slave select input) pb5 output input mosi (spi bus master output/slave input) pb6 input output/hi-z miso (spi bus master input/slave output) pb7 output input sck (spi bus serial clock) table 7-6. port b pins alternate functions port pin direction alternate function bit field default avr description 7msb 0r/w it is an 8-bit r/w register with a 0 initial value 0xff. the bits in the data direction register control the direction of the corresponding pin in port b when bit ddrbx is set, then pbx pin is input, while when ddrbx is cleared, the pbx is output (x = 0?7) 60r/w 50r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w bit field default avr description 7msb 0r/w the bits in the data direction register control the direction of the corresponding pin in port b. when bit ddrbx is set, then the pbx pin is output, while when ddrbx is cleared, the pbx pin is input (x = 0..7) 60r/w 50r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w
67 5665b?usb?04/05 AT76C713 atmel confidential port b input pins address (pinb) addr $16 ($36) 8 bits 7.6.3 port c port c is a 8-bit output port with internal pull-up resistors. 7.6.3.1 port c alternative functionality in addition to functioning as a general-purpose i/o port, port c is used to support alternate functions. specifically, it is used as the addr ess bus a[8-14]and ale of the external memory interface. 7.6.3.2 port c i/o regsiters port c data register (portc) addr $15 ($35) 8 bits port c data direction register addr $14 ($34) 8 bits bit field default avr description 7msb n/ar the port b input pins address (pinb) is not a physical register. this address enables access to the physical voltage value on each port pin. it is a read-only address. the initial value of pinb depends from st atus of each port b pin 6n/ar 5n/ar 4n/ar 3n/ar 2n/ar 1n/ar 0lsb n/ar bit field default avr description 7 msb 0 r/w it is an 8-bit r/w register with zero initial value 0xff. the bits in the data direction register control the direction of the corresponding pin in the port c when bit ddrbx is set, then pbx pin is input, while when ddrbx is cleared pbx is output, x = 0?7 6:1 0 r/w 0lsb 0r/w bit field default avr description 7 msb 0 r/w the bits in the data direction register controls the direction of the corresponding pin in the port c when bit ddrcx is set, then pcx pin is output, while when the ddrcx is cleared, the pcx pin is input (x = 0..7) 6:1 0 r/w 0lsb 0r/w
68 5665b?usb?04/05 AT76C713 atmel confidential port c input pins address (pinc) addr $13 ($33) 8 bits 7.6.4 port d port d is an 8-bit bi-directional i/o port with internal pull-up resistors. 7.6.4.1 port d alternative functionality in addition to functioning as a general-purpose i/o port, port d is used to support alternate functions. specifically, it offers t he signals of uart0, as shown in table 7-7 . also, when the uart0 is enabled, the data direction of the port d pins is overridden, according to table 7-7 . port d pins use the special pad ?vdd for portd? for a power supply. 7.6.4.2 port d i/o registers port d data register (portd) addr $12 ($32) 8 bits bit field default avr description 7msb n/ar the port c input pins address (pinc) is not a physical register. this address enables access to the physical voltage value on each port pin. it is a read-only address. the initial value of pinc depends on the st atus of each port c pin 6:1 n/a r 0lsb n/ar table 7-7. port d pins alternate functions port pin direction alternate function pd0 input serial receive in uart0 pd1 output serial transmit out uart0 pd2 bi-directional nrts, uart0 ready to send pd3 bi-directional ncts, uart0 clear to send pd4 bi-directional ndsr, uart0 data set ready pd5 bi-directional ndtr, uart0 data terminal ready pd6 bi-directional ncd, uart0 carrier detect pd7 bi-directional nri, uart0 ring indicator bit field default avr description 7 msb 0 r/w it is an 8-bit r/w register with zero initial value 0xff. the bits in the data direction register control the direction of the corresponding pin in the port d. when bit ddrbx is set, then pbx pin is input, while when ddrbx is cleared pbx is output (x = 0?7) 6:1 0 r/w 0lsb 0r/w
69 5665b?usb?04/05 AT76C713 atmel confidential port d data direction register addr $11 ($31) 8 bits port d input pins address (pind) addr $10 ($30) 8 bits 7.6.5 port e port e is an 8-bit bi-directional i/o port with in ternal pull-up resistors at pins pe0, pe1, and pe4..7, and internal pull-down resistors at pins pe2 and pe3. 7.6.5.1 port e alternative functionality in addition to functioning as a general-purpose i/o port, port e is also used to support alter- nate functions. specifically, serves also as the tx/rx signals of uart1, as external interrupts and read/write signals for the external memory interface. when an alternative function is enabled, the data direction of port e pins is overridden, according to table 7-8 . bit field default avr description 7 msb 0 r/w the data direction register controls the direction of the corresponding pin in the port d when bit ddrdx is set, then the pdx pin is input, while when ddrdx is cleared, the pd x pin is output (x = 0?7) 6:1 0 r/w 0lsb 0r/w bit field default avr description 7 msb n/a r the port d input pins address (pind) is not a physical register. this address enab les access to the physical voltage value on each port pin. it is a read-only address. the initial value of pind depends on the status of each port d pin 6:1 n/a r 0lsb n/ar table 7-8. port e pins alternate functions port pin direction alternate function pe0 input serial receive in uart1 pe1 output serial transmit out uart1 pe2 (ddre) int0: edge triggered or level sensitive interrupt with pull-down pe3 (ddre) int1: edge triggered or level sensitive interrupt with pull-down pe4 (ddre) int2: edge triggered or level sensitive interrupt with pull-up pe5 (ddre) int3: edge triggered or level sensitive interrupt with pull-up pe6 output nwr: write signal for the external memory interface pe7 output nrd: read signal for the external memory interface
70 5665b?usb?04/05 AT76C713 atmel confidential 7.6.5.2 port e i/o registers port e data register (porte) addr $0a ($2a) 8 bits port e data direct ion register (ddre) addr $09 ($29) 8 bits port e input pins address (pine) addr $08 ($28) 8 bits 8. memory space (register description) 8.1 usb register set the usb appears to the avr to be just another peripheral. the usb register file is mapped to the sram space. table 8-1 summarizes the usb cell specific registers. bit field default avr description 7 msb 0 r/w the bits in the data direction register control the direction of the corresponding pin in the port e when bit ddrbx is set, then pbx pin is input, while when ddrbx is cleared pbx is output, x = 0?7 6:1 0 r/w 0lsb 0r/w bit field default avr description 7 msb 0 r/w the bits in the data direction register control the direction of the corresponding pin in the port e when bit ddrex is set, then pex pin is output, when ddrex is cleared, the pex pin is input (x = 0..7). 6:1 0 r/w 0lsb 0r/w bit field default avr description 7 msb n/a r the port e input pins address (pine) is not a physical register. this address enab les access to the physical voltage value on each port pin. it is a read-only address. the initial value of pine depends from status of eachport e pin 6:1 n/a r 0lsb n/ar table 8-1. usb register set register address default function slp_mode $f000 00000000b sleep mode control irq_en $f001 00000000b master interrupt enable irq_stat $f002 00000000b master interrupt status res_stat $f003 00000000b reset status pair_en $f004 00000000b pair addressing enable usb_dma_adl $f005 00000000b dma address low
71 5665b?usb?04/05 AT76C713 atmel confidential usb_dma_adh $f006 00000000b dma address high usb_dma_len $f007 00000000b dma packet length requested usb_dma_ead $f008 00000000b dma target endpoint address usb_dma_plt $f009 00000000b dma packet length transferred usb_dma_en $f00a 00000000b dma enable fbyte_cnt7_h $f0a8 00000000b fifo by te count 7 register [10:8] fbyte_cnt6_h $f0a9 00000000b fifo by te count 6 register [10:8] fbyte_cnt5_h $f0aa 00000000b fifo by te count 5 register [10:8] fbyte_cnt4_h $f0ab 00000000b fifo by te count 4 register [10:8] fbyte_cnt3_h $f0ac 00000000b fifo by te count 3 register [10:8] fbyte_cnt2_h $f0ad 00000000b fifo by te count 2 register [10:8] fbyte_cnt1_h $f0ae 00000000b fifo by te count 1 register [10:8] fbyte_cnt0_h $f0af 00000000b fifo by te count 0 register [10:8] fbyte_cnt7_l $f0b8 00000000b fifo by te count 7 register [7:0] fbyte_cnt6_l $f0b9 00000000b fifo by te count 6 register [7:0] fbyte_cnt5_l $f0ba 00000000b fifo by te count 5 register [7:0] fbyte_cnt4_l $f0bb 00000000b fifo by te count 4 register [7:0] fbyte_cnt3_l $f0bc 00000000b fifo by te count 3 register [7:0] fbyte_cnt2_l $f0bd 00000000b fifo by te count 2 register [7:0] fbyte_cnt1_l $f0be 00000000b fifo by te count 1 register [7:0] fbyte_cnt0_l $f0bf 00000000b fifo by te count 0 register [7:0] fdr7 $f0c8 00000000b fifo 7 data register fdr6 $f0c9 00000000b fifo 6 data register fdr5 $f0ca 00000000b fifo 5 data register fdr4 $f0cb 00000000b fifo 4 data register fdr3 $f0cc 00000000b fifo 3 data register fdr2 $f0cd 00000000b fifo 2 data register fdr1 $f0ce 00000000b fifo 1 data register fdr0 $f0cf 00000000b fifo 0 data register ecsr7 $f0d8 x1110000b endpoint7 control and status register ecsr6 $f0d9 x1110000b endpoint6 control and status register ecsr5 $f0da x1110000b endpoint5 control and status register ecsr4 $f0db x1110000b endpoint4 control and status register ecsr3 $f0dc x1110000b endpoint3 control and status register ecsr2 $f0dd x1110000b endpoint2 control and status register ecsr1 $f0de x1110000b endpoint1 control and status register table 8-1. usb register set (continued) register address default function
72 5665b?usb?04/05 AT76C713 atmel confidential slp_mode (sleep mode control register) addr: $f000 8 bits irq_en (usb interrupt mask register) addr: $f001 8 bits ecsr0 $f0df x1110000b endpoint0 control and status register ecr7 $f0e8 0xxx0000b endpoi nt7 control register ecr6 $f0e9 0xxx0000b endpoi nt6 control register ecr5 $f0ea 0xxx0000b endpoi nt5 control register ecr4 $f0eb 0xxx0000b endpoi nt4 control register ecr3 $f0ec 0xxx0000b endpoi nt3 control register ecr2 $f0ec 0xxx0000b endpoi nt2 control register ecr1 $f0ee 0xxx0000b endpoi nt1 control register ecr0 $f0ef 0xxx0000b endpoi nt0 control register endppgpg $f0f1 00000000b function endpoint ping-pong register faddr $f0f2 00000000b function address register uier $f0f3 xxx00000b usb interrupt enable register uiar $f0f5 xxxxx000b usb interrupt acknowledge register uisr $f0f7 00000000b usb interrupt status register sprsie $f0f9 xxxxx000b suspe nd/resume interrupt enable register sprsr $f0fa xxxxx000b suspend/resume register glb_state $f0fb xxxxx000b g lobal stat e register frm_num_l $f0fc xxxxx000b frame number low register frm_num_h $f0fd xxxxx000b frame number high register bit field avr description 7:6 reserved reserved and set to 0 5 slp r/w if set, put the usb controller in sleep mode 4:0 reserved reserved and set to 0 bit field avr description 7 reserved r/w reserved and set to 0 6int_en r/w when this bit is high, enables the usb protocol handler to cause an interrupt (see uisr and irq_stat[6]) table 8-1. usb register set (continued) register address default function
73 5665b?usb?04/05 AT76C713 atmel confidential irq_stat (usb interrupt status register) the irq_stat register is automatically cleared on each read access. addr: $f002 8 bits res_stat (reset status) addr: $f003 8 bits 5:2 reserved r/w reserved and set to 0 1 susp_int_en r/w if this bit is high, an interrupt is generated when the usb enters suspend mode a usb device enters in suspend mode only when requested by the usb host through bus inactivity for at least 3 ms 0rsm_int_en r/w if this bit is high, an interrupt is generated when the usb enters resume mode. a j-to-k state change on the usb port signal resume bit field avr description 7 reserved r reserved and set to 0 6int r interrupt from the usb protocol handler. when this bit is high, then at least one bit of uisr is set 5:4 reserved r reserved and set to 0 3 usb_rst r this bit is high, while the usb bus remains in reset state. this bit can be accessed also by using the res_stat register, avoiding to clear the irq_stat 2 nsusp r when this bit is high, the usb has exited from the suspend mode 1 psusp r when this bit is high, the usb has entered the suspend mode 0 pusb_rst r when this bit is high, the usb host controller has sent a reset request (usb bus entered the reset state) bit field avr description 7:4 reserved r reserved and set to 0 3 usb_rst r this bit is high while the usb bus remains in reset state 2:0 reserved r reserved and set to 0 bit field avr description
74 5665b?usb?04/05 AT76C713 atmel confidential pair_en (pair addressing enable) addr: $f004 8 bits usb_dma_adl (dma address low) addr: $f005 8 bits usb_dma_adh (dma address high) addr: $f006 8 bits usb_dma_len (dma packet length) addr: $f007 8 bits bit field avr description 7:4 reserved r reserved and set to 0 3:1 upa[3:1] r/w by setting any of these bits, a pair of eps is formed of one in and one out. for example, if upa[1] is set, the ep1 should be configured as an out ep, while the ep4 as an in ep: upa[1]: ep4 has the same usb physical address with ep1 upa[2]: ep5 has the same usb physical address with ep2 upa[3]: ep6 has the same usb physical address with ep3 0 reserved r reserved and set to 0 bit field avr description 7:0 uda[7-0] r/w the least significant byte of the target address at the data memory that the dma controller will use bit field avr description 7 reserved r reserved and set to 0 6:0 uda[14-8] r/w these are seven bits along with the eight bits of the usb_dma_adl, form the ta rget address uda[14-0] at the data memory that the dma will use bit field avr description 7:0 plen[7-0] r/w the avr writes the nu mber of bytes fo r the next dma
75 5665b?usb?04/05 AT76C713 atmel confidential usb_dma_ead (dma target endpoint address) addr: $f008 8 bits usb_dma_plt (dma packet length transferred) addr: $f009 8 bits usb_dma_en (dma enable register) addr: $f00a 8 bits fbyte_cntx_h (fifo byte count high register) each endpoint has a register that stores the number of bytes to be sent or that was received by the usb h/w. the maximum data packet supported is 1024 bytes length for isochronous endpoints. addr: see table 8-1 bit field avr description 7:0 ead[7:0] r/w the avr writes the offset byte of the fdrx address, depending on the endpoint that is going to send or has received the data: the following endpoints with the corresponding offset bytes are supported by the dma channels: fdr1: $ce fdr2: $cd fdr3: $cc fdr4: $cb fdr5: $ca fdr6: $c9 fdr7: $c8 bit field avr description 7:0 tpl[7:0] r/w returns the number of bytes transferred during the last dma bit field avr description 7:2 reserved r reserved and set to 0 1 usb_rdma _en r/w enables receive dma (for out eps). this bit is automatically cleared after the end of the dma 0 usb_tdma_ en r/w enables transmit dma (for in eps ). this bit is automatically cleared after the end of the dma bit field avr description 7:3 reserved reserved reserved 2:0 bytecnt[10:8] r/w length of data packet in fifo
76 5665b?usb?04/05 AT76C713 atmel confidential fbyte_cntx_l (fifo byte count low register) addr: see table 8-1 fdr (fifo data registers 0 ?7) fifo data registers are dual function buffer regi sters. received data are read by the processor from the endpoint's fifo through these data regi sters. in the transmit mode, the processor writes to the fifo though this register. addr: see table 8-1 8 bits ecsr (endpoint control and status registers 0 ? 7) addr: see table 8-1 8 bits bit field avr description 7:0 bytecnt[7:0} r/w length of data packet in fifo bit field avr description 7:0 fifo data [7:0] r/w data to be written to fifo or data to be read from the fifo bit field avr description 7 control direction r this bit is set by the processor to indicate to the usb h/w the direction of a control transfer 0 = control write. no data stage 1 = control read this bit is used by control endpoints only and is used by fw to indicate the direction of a control transfer. it is written by the fw after it receives a rx setup interrupt. the h/w uses th is bit to determine the status phase of a control transfer 6 data end r this bit indicates that the processor has placed the last data packet in fifo0, or that the processor has processed the last data packet it expects from the host this bit is used only by control endpoints together with bit 1 (tx packet ready) to signal the usb h/w to go to the status phase after the packet currently residing in th e fifo is transmitted after the h/w completes the status pha se it will interrupt the processor without clearing this bit caution: because the data end bit signals ?end of transaction?, any other endpoint controller bit set after the data end is not considered by the ping-pong controller., which is why tx_packet ready should be set before data end 5 force stall r this bit is set by the processor to indicate a stalled endpoint. the h/w will send a stall handshake as a response to the next in or out token the processor sets this bit if it wa nts to force a stall if an unsupported request is received or if the host co ntinues to ask for data after the data is exhausted. this bit should be set at the end of any data phase or setup phase
77 5665b?usb?04/05 AT76C713 atmel confidential 4 tx packet ready r/c this bit indicates that the processor has loaded the fifo with a packet of data. this bit is cleared by the h/w after the usb host acknowledges the packet. for iso endpoints, this bit is cleared unconditionally after the data is sent this bit is used for the following operations : control read transactions by a control endpoint in transactions with data1 pid to complete the status phase for a control endpoint, when this bit is 0, but bit data end (bit 4) is 1 by a bulk in or iso in or int in endpoint the processor should write into the fifo only if this bit is cleared. after it has completed writing the data, it should set this bit. the data can be of 0 length. for a control endpoint, the proc essor should write to the fifo only when bit 6 (tx packet requested) is set. the h/w clears this bit after it receives an ack. if the interrupt is enabled, clearing this bit by the h/w causes an interrupt to the processor 3 stall snd w the usb h/w sets this bit after a stal l is sent to the host. the firmware uses this bit when responding to a usb getstatus request this bit indicates end of data stage for the control endpoint only 2 rx setup w the usb h/w sets this bit when it receives a valid setup packet from the host. this bit is used by control endpoints only to signal to the processor that the usb h/w has received a valid setup packet and that the data portion of the packet is stored in the fifo. the h/w will clear all other bits in this register and will set the rx set up. if the corresponding interrupt is enabled, the processor will be inte rrupted when the rx setup is set. after the completion of reading the data from the fifo, the firmware should clear this bit 1 rx out packet w this bit indicates that the usb h/w has decoded an out token and that the data is in the fifo. the usb h/w sets this bit after it has stored the data of an out transaction in the fifo. when this bit is set, the h/w will nak all out tokens. for control endpoints only, bit 7 of this register, enable control write, has to be set for the h/w to accept the out data. the usb h/w will not overwrite the data in the fifo except for an early usb setup request. bit rx out packet is used for the following operations: control write transactions by a control endpoint out transaction with data1 pid to complete the status phase of a controlendpoint by a bulk out or iso out or int out endpoint setting this bit causes an interrupt to the processor if the interrupt is enabled. the firmware clears this bit after the fifo is read 0 tx complete r the h/w sets this bit to indicate to a control endpoint that it has received an ack handshake from the host. this bit is used by h/w in a control endpoint to signal to the processor that it has successfully completed certain transactions. tx complete is set at the completion of a: control read data stage status stage without data stage status stage after a control write transaction bit field avr description
78 5665b?usb?04/05 AT76C713 atmel confidential ecr (endpoint control registers 0 ?7) addr: see table 8-1 8 bits endppgpg (endpoint ping- pong enable register) addr: $f0f1 8 bits bit field avr description 7 epeds r endpoint enable/disable (0 = disable endpoint, 1 = enable endpoint) 6 reserved r reserved 5:4 reserved reserved and set to 0 3 dtgle w data toggle. identifies data0 or data1 packets 2 epdir r endpoint direction only applicable for non-control endpoints (0 = out, 1 = in) 1:0 eptype r endpoint type these bits represent the type of the endpoint as follows: bit1 bit0 type 0 0 control 0 1 isochronous 1 0 bulk 1 1 interrupt bit field avr description 7 reserved 6 pg pg 6 en r enable endpoint 6 ping-pong 5 pg pg 5 en r enable endpoint 5 ping-pong 4 pg pg 4 en r enable endpoint 4 ping-pong 3 pg pg 3 en r enable endpoint 3 ping-pong 2 pg pg 2 en r enable endpoint 2 ping-pong 1 pg pg 1 en r enable endpoint 1 ping-pong 0 pg pg 0 en r enable endpoint 0 ping-pong
79 5665b?usb?04/05 AT76C713 atmel confidential faddr (function address register) addr: $f0f2 8 bits uier (usb interrupt enable register) addr: $f0f3 8 bits table 1. bit field avr description 7fenr function enable the fiu contains an address re gister that contains the function address assigned by the host. the function address register must be programmed by the processor once it ha s received a set_address command from the host and completed the status phase of the transaction. after power up or reset, this register will contain the va lue of 0x00. the function enable bit (fen) allows the firmware to enable or disable the function endpoints. the firmware will set this bit after receipt of a reset through the usb h/w. once this bit is set, the usb h/w passes packets to and from the host 6:0 fadd[6:0] r function address bit field avr description 7 sof ie r enable sof interrupt the bits in this register have the following meaning: 1 = enable interrupt 0 = disable interrupt 6 ep6 ie r enable endpoint 6 interrupt 5 ep5 ie r enable endpoint 5 interrupt 4 ep4 ie r enable endpoint 4 interrupt 3 ep3 ie r enable endpoint 3 interrupt 2 ep2 ie r enable endpoint 2 interrupt 1 ep1 ie r enable endpoint 1 interrupt 0 ep0 ie r enable endpoint 0 interrupt
80 5665b?usb?04/05 AT76C713 atmel confidential uiar (usb interrupt acknowledge register) addr: $f0f5 8 bits uisr (usb interrupt status register) addr: $f0f7 8 bits bit field avr description 7reserved the bits in this register are used to indirectly clear the bits of the uisr. a bit in the uisr is cleared if a 1 is written in the corresponding bit of uiar 6 ep6 inta w endpoint 6 interrupt acknowledge 5 ep5 inta w endpoint 5 interrupt acknowledge 4 ep4 inta w endpoint 4 interrupt acknowledge 3 ep3 inta w endpoint 3 interrupt acknowledge 2 ep2 inta w endpoint 2 interrupt acknowledge 1 ep1 inta w endpoint 1 interrupt acknowledge 0 ep0 inta w endpoint 0 interrupt acknowledge bit field avr description 7 reserved the function interrupt bits will be set by the h/w whenever the following bits in the corresponding endpoint's control and status register are modified by the usb h/w: rx out packet is set (control and out endpoints) tx packet ready is cleared (control and in endpoints) rx setup is set (control endpoints only) tx complete is set (control endpoints only) 6 ep6 int w endpoint 6 interrupt 5 ep5 int w endpoint 5 interrupt 4 ep4 int w endpoint 4 interrupt 3 ep3 int w endpoint 3 interrupt 2 ep2 int w endpoint 2 interrupt 1 ep1 int w endpoint 1 interrupt 0 ep0 int w endpoint 0 interrupt
81 5665b?usb?04/05 AT76C713 atmel confidential sprsie (suspend/resume interrupt enable register) addr: $f0f9 8 bits sprsr (suspend/resume register) addr: $f0fa 8 bits glb_state (global state register) addr: $f0fb 8 bits bit field avr description 7:4 reserved 3 sof ie r enable sof interrupt 2extrsm ier enable external resume signaling interrupt 1 = enable 0 = disable 1 rcvdrsm ie r enable bus resume signaling interrupt 1 = enable 0 = disable 0 susp ie r enable suspend signaling interrupt 1 = enable 0 = disable bit field avr description 7:4 reserved 3 sof int r/w start of frame interrupt. firmware clears this bit to acknowledge the sof interrupt. 2 ext rsm r/w received external resume. the usb h/w sets this bit to denote an external resume interrupt. if rmwupe =1, a resume signal is send in usb bus. firmware clears this bit to acknowledge the ext rsm interrupt. 1 rcvd rsm r/w received resume. the usb h/w sets this bit when a usb resume signaling is detected at its port. firmware clears this bit to acknowledge the rcvd rsm interrupt. 0susp r/w suspend. the usb h/w sets this bit when it detects no sof for 3ms. the usb macro enters in suspend mode, the processor has to go in sleep mode.firmware clears this bit to acknowledge the susp interrupt. bit field avr description 7:4 reserved reserved 3 rsminpr w set by the h/w when a resume is send in the usb bus during remote wake-up feature (13 ms)
82 5665b?usb?04/05 AT76C713 atmel confidential frm_num_l (frame number low register) addr: $f0fc 8 bits frm_num_h (frame number high register) addr: $f0fd 8 bits 8.2 uart register set the base address for uart0 registers is $f200 and for uart1 registers is $f300. each read or write access of the uart registers consumes at least 2 cpu cycles, since the uart core clock is asynchronous and fixed to 14.769 mhz. the register file and its fields are briefly pres ented in table 26. a more detailed description is provided in the following sections. 2rmwuper remote wake-up enable. this bit is set if the host enables the function's remo te wake-up feature 1confgr configured. this bit is set by the firmware after a valid set_configuration request is received. it is cleared by a reset or by a set_configuration with a value of 0 0 fadd enable r function address enable. this bit is set by firmware after the status phase of a set_adress request transaction. the host will use the new address starting at the next transaction bit field avr description 7:0 fcl[7:0] w this is the lower 8-bits of the 11 bit frame number of sof packet bit field avr description 7:3 reserved reserved and set to 0 2:0 fch[10:8] w this is the upper 3 bits of the 11 bit frame number of sof packet bit field avr description table 8-2. uart register file and register fields addr a[3:0] register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general register set 0000 dlab = 0 rhr msb lsb 00000 dlab = 0 thr msb lsb
83 5665b?usb?04/05 AT76C713 atmel confidential receive holding register (rhr) addr: $0000 8 bits 0001 dlab = 0 ier0000 enable modem status interrupt enable rx line status interrupt enable thr ready interrupt enable rx data available interrupt 0010 iir fifo enabled fifo enabled 00 interrupt id bit 2 interrupt id bit 1 interrupt id bit 0 not interrupt pending 0010 fcr rx fifo trigger msb rx fifo trigger lsb 00 dma mode tx fifo reset rx fifo reset fifo enable 0011 lcr divisor latch access (dlab) set break stick parity even parity enable parity number of stop bits word length bit 1 word length bit 0 0100 mcr 0 0 0 loopback out2 out1 rts dtr 0101 lsr error in rx fifo transmitte r empty thr ready break interrupt framing error parity error overrun error rx data available 0110 msr cd ri dsr cts delta cd trailing edge ri delta dsr delta cts 0111 scr msb lsb special register set 0000 dlab = 1 dll msb lsb 0001 dlab = 1 dlh msb lsb 1000 xr1 output pins in loopback send address start time-out control restart time-out tx reset rx reset tx disable rx disable 1001 xr2 tx fifo disable transmitte r empty thr ready thr ready bit control 000 multi- drop 1010 mdr ncd pin direction nri pin direction ndsr pin direction ncts pin direction nout2 pin direction nout1 pin direction nrts pin direction ndtr pin direction 1011 rto msb lsb 1100 ttg msb lsb table 8-2. uart register file and register fields (continued) bit field default avr description 7msb 0 r this bit holds the received byte 6:1 0 r 0lsb 0r
84 5665b?usb?04/05 AT76C713 atmel confidential transmit holding register (thr) addr: $0000 8 bits interrupt enable register (ier) addr: $0001 8 bits interrupt identification register (iir) addr: $0010 8bits bit field default avr description 7msb 0 w this bit holds the byte to be transmitted 6:1 0 w 0lsb 0w bit field default avr description 7:4 ? 0 r/w ? 3 msi: enable modem status interrupt 0r/w if this bit is set, it enables the modem status interrupt (msr[7:4]) 2 rlsi: enable receive line status interrupt 0 r/w if this bit is set, it enables the line status interrupt (lsr[4:1]) 1 tri: enable thr ready interrupt 0 r/w if this bit is set, it enables the thr ready interrupt (lsr[5]) 0 rdai: enable rx data available interrupt 0r/w if this bit is set, it enables the rx data available interrupt. it also enables the time-out interrupt when the time-out counter is enabled (in fifo mode or if rto is not 0, see xr1[5] and rto) bit field default avr description 7:6 fifoen: fifo enabled 0 r these two bits are set when fcr[0] is set 5:4 ? 0 r ? 3 id2 0 r interrupt id bit 2
85 5665b?usb?04/05 AT76C713 atmel confidential fifo control register (fcr) addr: $0010 8 bits 2 id1 0 r interrupt id bit 1 1 id0 0 r interrupt id bit 0 0 nip:not interrupt pending 0r when this bit is in logic 0, then an interrupt is pending and the iir[3..1] bits may be used for interrupt type identification. when this bit is in logic 1, no interrupt is pending table 8-3. uart interrupt priority priority id2 id1 id0 interrupt source (event) interrupt reset control highest 0 1 1 receiver line status (lsr[3..1] not 0) reading lsr 0 1 0 received data available reading all the data from the receive holding register or the rx fifo 1 1 0 time-out indication reading the rhr or receiving a new word from sin pin 001 transmitter holding register ready reading iir or writing to thr lowest000 modem status (when any bit in msr[7..4] changes from ?0? to ?1?). reading msr bit field default avr description 7 rcvr1 0 w rcvr trigger bits. these bits indicate the minimum number of bytes required in the receive fifo to generate a receive ready interrupt. the trigger level is shown from the following table 6 rcvr0 0 w 5:4 ? 0 w ? 3 rdma: dma mode select 0w when fifos are disabled (fcr[0] is low), this bit is forced to 0. when set to logic 1, the dma is in burst mode allowing transfers until the rx fifo ha s been emitted or the tx fifo has been filled. when it is cleared to 0, the dma is in single mode and the words are read one word at a time bit field default avr description bit 7 bit 6 trigger level (words) 00 1 01 4 10 8 11 14
86 5665b?usb?04/05 AT76C713 atmel confidential line control register (lcr) addr: $0011 8 bits 2 trs:tx fifo reset 0 w when this bit is set, it resets the transmit fifo 1 frs: rx fifo rese t 0 w when this bit is set, it resets the receive fifo 0 fen:fifo enable 0w when this bit is set, it enables the 16-byte receive and transmit fifos. when this bi t is cleared, the fifos are disabled and reset bit field default avr description 7 dlab: divisor latch access 0r/w this bit must be set to logic 1 during a read or write operation in order to access the divisor latches. resetting this bit to 0 allows access to rhr, thr, and ier 6 sbrk: set break 0r/w if this bit is set, then it ca uses a break condition to to be transmitted to the receiving uart. the sout pin is forced to the spacing state (logic 0). re setting to logic 0 stops the break condition. the break control bit acts only on sout pin and has no effect on the transmitter logic. note that uart waits before starting the break condition command for the complete transmission of the word in the transmit shift register. there is no need for software synchronization 5 spar: stick parity 0r/w when the parity enable and the parity stick bits are set to logic 1, then the even parity bit controls the transmitted parity value. by resetting the even parity bit to logic 0, the parity bit is transmitted and checked as 1. by setting the even parity bit to logic 1, the parity bit is transmitted and checked as 0 4 evpar: even parity 0r/w when the enable parity bit is a 1 and the stick parity bit is a 0, then by setting to the even parity bit o 1 an even number of logic 1s is transmitted or checked in the data word bits and the parity bit. when even parity bit is reset to logic 0, an odd number of 1s are transmitted or checked 3 enpar: enable parity 0r/w by setting this bit to logic 1, a parity bit is transmitted or checked. resetting this bit to 0, no parity bit is transmitted or checked bit field default avr description
87 5665b?usb?04/05 AT76C713 atmel confidential modem control register (mcr) addr: $0100 8 bits 2 sb: number of stop bits 0r/w this bit determines the number of stop bits according to the following table: 1 wl1: word length 0r/w these bits determine the word length according to the following table 0 wl0: word length 0r/w bit field default avr description 7:5 ? 0 r/w 4 lb: loopback 0r/w if this bit is set, it enables the loopback mode. this bit cannot be set to logic 1 if the value of mdr is not $f0 3 out2 0 r/w the compliment value of the bi-directional pin nout2 2 out1 0 r/w the compliment value of the bi-directional pin nout1 1 rts 0 r/w the compliment value of the bi-directional pin nrts 0 dtr 0 r/w the compliment value of the bi-directional pin ndtr bit field default avr description bit 2 word length number of stop bits 0any 1 15 1,5 1 6, 7, 8 2 bit 1 bit 0 word length (bits) 00 5 01 6 10 7 11 8
88 5665b?usb?04/05 AT76C713 atmel confidential line status register (lsr) addr: $0101 8 bits bit field default avr description 7 erf: error in rx fifo 0r if the fifos are disabled, this bit is a 0. if the fifos are enabled, this bit indicates that at least one word in the rx fifo has its parity error, framing error, or break indication bits high 6 te: transmitter empty 0r if set, this bit indicates that both the transmit shift register and transmit holding register, or the tx fifo if tx fifo is enabled, are empty 5 thrr: transmit holding register ready 0r if set, this bit indi cates that the thr is ready to accept a new word for transmission. this bit is set when a word is transferred from the thr into the tx shift register. this bit is reset concurrently with the loading of the thr by the core. if the tx fifo is enabled (fcr[0] = 1, xr2[7] = 0), the function of this bit is controlled by xr2[4]. if xr2[4] is 0, then this bit is set when the tx fifo is empty; it is cleared when at least 1 word is written to the tx fifo. if xr2[4] is 1, then this bit is set when the tx fifo is not full 4 bi: receive break interrupt 0r if set, this bit indicates a brea k interrupt that the receive data input is held in the spacing state (logic 0) for longer than a full word transmission time.in fifo mode, this error is associated with the word at the top of the rx fifo which is equivalent to rhr. this bit is reset to a logic 0 whenever the core reads the lsr 3 fe: framing error 0r if set, this bit indicates a fram ing error. the received word in rhr does not have the correct stop bit. in fifo mode, this error is associated with the word at the top of the rx fifo which is equivalent to rhr. this bit is reset to a logic 0 whenever the core reads the lsr 2 pe:parity error 0r if set, this bit indicates a pari ty error. the received word in rhr does not have the correct parity bit. in fifo mode, this error is associated with the word at the top of the fifo which is equivalent to rhr. this bit is reset to a logic 0 whenever the core reads the lsr 1 oe:overrun error 0r if set, this bit indicates an ov errun error, that is, the data in rhr was not read by the core before the next word was transferred into the rhr, thereby destroying the previous word. in fifo mode, an overrun error will occur only after the rx fifo is full and the next word has been completely received in the shift register. the word in the shift register is overwritten, but it is not transferred to the rx fifo. the overrun error is indicated to the core as soon as it happens. this bit is reset to a logic 0 whenever the core reads the lsr 0 rda: receive holding register ready 0r if set, this bit indicates that there is data available in the rhr. this bit resets to logic 0 by reading all of the data from the receive holding register or the rx fifo
89 5665b?usb?04/05 AT76C713 atmel confidential modem status register (msr) addr: $0110 8 bits scratch-pad register (scr) addr: $0111 8 bits divisor latch register, low byte (dll) addr: $0000 8 bits bit field default avr description 7cd 0r/w the compliment of the bi-dir ectional carrier detect ncd i/o pin. if mcr[4] is set (loopback mode), then this bit is equivalent to nout2 pin 6ri 0r/w the compliment of the bi-directional ring indicator nri i/o pin. if mcr[4] is set (loopback mode),then this bit is equivalent to nout1 pin 5dsr 0r/w the compliment of the bi-directional data set ready ndsr i/o pin. if mcr[4] is set (loopback mode), then this bit is equivalent to ndtr pin 4cts 0r/w the compliment of the bi-directional clear to send ncts i/o pin. if mcr[4] is set (loopback mode), then this bit is equivalent to nrts pin 3 dcd: delta carrier detect indicator 0r/w this bit indicates that the ncd pin has changed state since the last time it was read by the core 2 tri: trailing edge of ring indicator 0r/w this bit indicates that the nri pin has changed from a low to a high state since the last time it was read by the core 1 ddsr: delta data set ready indicator 0r/w this bit indicates that the ndsr pin has changed states since the last time it was read by the core 0 dcts: delta clear to send indicator 0r/w this bit indicates that the ncts pin has changed states since the last time it was read by the core bit field default avr description 7msb 0r/w a scratch-pad register which holds data temporarily. doe not effect the uart 6:1 0 r/w 0lsb 0r/w bit field default avr description 7msb 0r/w baud rate generator division ratio low byte 6:1 0 r/w 0lsb 0r/w
90 5665b?usb?04/05 AT76C713 atmel confidential divisor latch register, high byte (dlh) addr: $0001 8 bits extra register 1 (xr1) addr: $1000 8 bits note: when xr1 and xr2 registers are both $00, then the uart operates in 16550 compatible mode. bit field default avr description 7 msb 0 r/w baud rate generator division ratio high byte the main uart clock, from th e system clock generator, is divided by the 16-bit number contained in dll and dlh, to provide the uart clock (which is 16 times the actual serial data rate) 6:1 0 r/w 0lsb 0r/w bit field default avr description 7 opl:output pins in loopback 0r/w if this bit is set in loopback mode (mcr[4] is set), then the sout, nout2, nout1, nrts, and ndtr pins are not forced to logic 1. instead, these pins operate normally (echo). if the loopback mode is disabled, then this bit has no effect 6 sa:send address 0r/w effective in multidrop mode on ly (see xr2[0]). if set, the next word will be transmitted with the parity bit (in multidrop mode, this is called address bit) forced at logic 1 5 stoc: start time- out control 0r/w this bit controls the start oper ation of the time-out counter. if set in logic 0, then it oper ates in 16550 compatible mode. if set in logic 1, the time-out counter starts whenever rto is not 0 (see and rto) 4 rto: restart time-out 0r/w writing a logic 1 resets the time-out counter. this bit resets to logic 0 automatically 3 txr: tx reset 0r/w writing a logic 1 resets the transmit path (and tx fifo). this bit resets to logic 0 automatically 2 rxr: rx reset 0r/w writing a logic 1 resets the receive path (and rx fifo). this bit resets to logic 0 automatically 1 txdis: tx disable 0 r/w if this bit is set, it disables the transmit path 0 rxdis: rx disable 0 r/w if this bit is set, it disables the receive path
91 5665b?usb?04/05 AT76C713 atmel confidential extra register 2 (xr2) addr: $1001 8 bits note: when xr1 and xr2 registers are both $00, then the uart operates in 16550 compatible mode. modem direction register (mdr) addr: $1010 8 bits bit field default avr description 7 txfd:tx fifo disable 0r/w if this bit is set, it disables the tx fifo. so, if fcr[0] and xr2[7] are both set, then onl y the rx fifo is enabled 6 te : tr a n s m i t t e r empty 0r/w this bit is equivalent to lsr[6]. it can be used to check if the transmitter is empty without resetting the error bits in lsr 5 thrr: thr ready 0r/w this bit is equivalent to lsr[5]. it can be used to check if the thr is ready to load data without resetting the line status bits in lsr 4 thrrc:thr ready bit control 0r/w functional only if tx fifo is enab led. if set in logic 0, then the lsr[5] (and xr2[5]) bit indicates that tx fifo is empty (thrr bit is 1) or that it has at least one word waiting for transmission (thrr bit is 0). setting this bit to logic 1, then lsr[5] (and xr2[ 5]) bit indicates that tx fifo is not full (thrr bit is 1) or that it is full (thrr bit is 0) 3:1 ? 0 r/w ? 0 mdm: multidrop mode 0r/w if set, this bit enables the multidrop mode. in this case, the parity error bit in lsr is set when data is detected with the parity bit at logic 1 to identify an address word. if the received parity bit is detected low, then the parity error bit is not set. the transmitter sends an address word (with the parity bit set) when the send address bit (xr1[6]) is set. setting the xr1[6] the next word written to thr will be transmitted as an address and any transmitted word after this will have the parity bit cleared bit field default avr description 7 ncdd:ncd pin direction 1 r/w if this bit is set, the ncd pin is configured as input 6 nrid:nri pin direction 1 r/w if this bit is set, the nr i pin is configured as input 5 ndsrd:ndsr pin direction 1 r/w if this bit is set, the t nd sr pin is configured as input 4 nctsd:ncts pin direction 1 r/w if this bit is set, the nc ts pin is configured as input 3 nout2d:nou t2 pin direction 0 r/w if this bit is set, the nout2 pin is configured as input
92 5665b?usb?04/05 AT76C713 atmel confidential receiver time-out register (rto) addr: $1011 8 bits transmitter time guard register (ttg) addr: $1100 8 bits 2 nout1d:nou t1 pin direction 0 r/w if this bit is set. the nout1 pin is configured as input 1 nrtsd:nrts pin direction 0 r/w if this bit is set, the nrts pin is configured as input 0 ndtrd:ndtr pin direction 0 r/w if this bit is set, the nd tr pin is configured as input bit field default avr description 7 msb 0 r/w this register contains the maximum bit periods, for which the uart will wait the next word to arrive. whenever the time-out counter expires, then a time-out indication interrupt will be issued the xr1[5] start time-out control bit selects the start time- out and rto load mechanism. if the xr1[5] bit is reset to 0 (16550 compatible mode), then the rto loads the value 4 times the word length + 12 on each lcr write operation. after reset, the word length is 5 bits and the rto is $20. the time- out counter will then start counting down only in fifo mode (fcr[0] is set) and if the rx fifo holds at least 1 word. if xr1[5] is set to 1, then the time -out function is available and in fifo disabled mode. the rto value does not change with lcr write operations. the time- out counter will start counting down whenever the rto is not $00 and the rhr is loaded. in all cases core has immediat e access at the contents of the rto. the time-out counter resets wh en a new word is completely received and transferred at the receive holding register or when the xr1[4] bit is forced to logic 1. if xr1[5] is reset to 0, time-out counter resets and on a rhr read access from core 60r/w 51r/w 40r/w 30r/w 20r/w 10r/w 0lsb 0r/w bit field default avr description 7msb 0 r/w the value of this register indicates the delay (in bit periods) that an active transmitter has to interpose between two consecutive word transmissions 6:1 0 r/w 0lsb 0r/w bit field default avr description
93 5665b?usb?04/05 AT76C713 atmel confidential 8.3 memory access interface register set memory bank map register (memmap) addr: $f800 8 bits table 8-4. baud rate generation example (uart clock = 14,769 mhz) output baud rate user devisor (16*cl k) ubm value ubl value decimal hex hex hex 100 9216 2400 24 00 200 4608 1200 12 00 400 2304 900 09 00 600 1536 600 06 00 1200 768 300 03 00 2400 384 180 01 80 4800 192 c0 00 c0 9600 96 60 00 60 14400 64 40 00 40 19200 48 30 00 30 28800 32 20 00 20 38400 24 18 00 18 57600 16 10 00 10 76800 12 0c 00 0c 115200 8 08 00 08 153600 6 06 00 06 230400 4 4 00 04 307200 3 03 00 03 460800 2 02 00 02 921600 1 01 00 01 bit field default avr description 7msb 0 r/w utilizing the memmap register, it is possible to resize the two memory spaces 6:1 0 r/w 0lsb 1r/w
94 5665b?usb?04/05 AT76C713 atmel confidential dma external memory interface control register a (dma_emicra) addr: $f801 8 bits dma external memory interface control register b (dma_emicrb) addr: $f802 8 bits bit field default avr description 7rw1 0 r/w read wait states: these bits cont rol the wait states inserted in the corresponding (read, write, and ale) signals 6rw0 0 r/w 5rm1 0r/w read mode select: these bits control the mode (waveform) of the corresponding (read, write, and ale) signals 4rm0 0r/w 3ww1 0 r/w write wait states:these bits cont rol the wait states inserted in the corresponding (read, write, and ale) signals 2ww0 0 r/w 1wm1 0 r/w write mode select: these bits c ontrol the mode (waveform) of the corresponding (read, write, and ale) signals 0wm0 0 r/w bit field default avr description 7aw1 0r/w ale wait states: these bits cont rol the wait states inserted in the corresponding (read, write, and ale) signals 6aw0 0r/w 5am1 0r/w ale mode select: these bits control the mode (waveform) of the corresponding (read, write, and ale) signals 4am0 0r/w 3? 0r/w these bits are reserved and must be remain always in 0 value 2? 0r/w 1 emd0 0 r/w external memory device select: these bits select the external memory interface mode according to the following table: 0emd1 0 r/w emd1 emd0 external memory interface mode 0 0 fifo 01 reserved 1 0 demultiplexed 1 1 multiplexed
95 5665b?usb?04/05 AT76C713 atmel confidential 9. errata 1. stack pointer is 11-bits wide the stack pointer is 11-bits wide. problem fix/workaround keep the stack below the address $07ff. 2. ddrb initial value the boostrap rom code, after accessing the external spi memory and remmaping to the final code, leaves the ddrb register to $10 value (instead of $00). the result is to have the ?pb4/nss? pin as output and set to 0 value ( because portb = $00). problem fix/workaround set the correct value of the ddrb register according to the given system configuration. 3.usb ?setup? packet in some cases the usb controller might not respond to a ?setup? packet if the previous usb packet was a ?status-in? and the firmware performed an action while servicing the packet. problem fix/workaround the firmware must wait for the next ?sof? packet before servicing the ?status-in? packet. the ?set address? is the only usb standard request that needs this special treatment. 4. iir and msr uart registers the iir register indicates when any bit in msr[7..4] is changed from 0 to 1 but it does not indi- cate a transition from 1 to 0. problem fix/workaround the firmware needs to poll the msr register in order to detect if any bit in msr[7..4] changes its value from 1 to 0. 5.unserved uart tx interrupt request the problem arises when both receive (rx) and transmit (tx) irqs are enabled and both rx and tx irqs are pending. in that case the firmwar e detects the rx irq when it reads the iir. this iir read though, may erroneously clear the tx irq. thus, the firmware loses the tx irq, which is never served. problem fix / workaround the uart interrupt service routine (isr) must examine and serve a potential tx irq, inde- pendently from the iir value. for example, the isr can use either the lsr[5] or the xr2[5] bits to check for pending tx irqs.
96 5665b?usb?04/05 AT76C713 atmel confidential 10. electrical specifications 10.2 d.c. characteristics 10.1 absolute maximum ratings operating temperature ......................................-40c to 85c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or other con- ditions beyond those indicated in the operational sections of this specification is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ........................................-65c to 150c voltage on any pin with respect to ground ..... 0v to maximum operating voltage maximum operating voltage ............................................ 3.6v 10.2.1 power supply symbol parameter condition min type max unit cvdd core supply voltage 1.65 1.8 1.95 v pvdd periphery supply voltage cvdd 3.3 cvdd + 1.5, 3.6 max v pvdd_usb usb supply voltage 3.0 3.3 3.6 v pavdd analog power supply 1.65 1.8 1.95 v v il low level input voltage -0.3 +0.8 v v ih high level input voltage 2.0 pvdd + 0.3 v v ol low level output voltage i ol = 0ma 0.2 v i ol = 2ma 0.4 v v oh high level output voltage i oh = 0ma pvdd - 0.2 v i oh = 2ma pvdd - 0.4 v 10.2.2 pull-up circuit (where pin = 0v) condition min max current pvdd = 3.3v 129a (pvdd = 3.0v) 322a (pvdd = 3.6v) current pvdd = 1.8v 30a (pvdd = 1.65v) 92a (pvdd = 1.95v) 10.2.3 pull-down circuit (where pin = pvdd) condition min max current pvdd = 3.3v 110a (pvdd = 3.0v) 356a (pvdd = 3.6v) current pvdd = 1.8v 27a (pvdd = 1.65v) 106a (pvdd = 1.95v)
97 5665b?usb?04/05 AT76C713 atmel confidential 10.3 ordering information 10.2.4 usb signals: dp, dm code parameter pu33b11f unit vt+ high level input voltage 1.8 v vt- low level input voltage 0.8 v vhys hysteresis 0.2 v 10.2.5 oscillator signals: osc symbol parameter condi tion min typ max unit pavdd supply voltage see standard operating conditions below 1.65 1.8 1.95 v supply ripple rms value, 10 khz to 10 mhz 30 mv idd on current consumption @16 mhz 0.9 1.6 ma freq operating frequency 8 12 16 mhz duty duty cycle 40 60 % ton startup time with crystal defined below 2ms pon drive level 150 w esr equivalent serie resistance @16 mhz 80 ? cm motional capacitance 5 9 ff cshunt shunt capacitance 7pf cload load capacitance max. external capacitors:40pf 15 20 pf idd stdby standby current consumption onosc = 0 1 a ? v dd device ordering code package AT76C713 AT76C713 100 lead tqfp
98 5665b?usb?04/05 AT76C713 atmel confidential 11. packaging information 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100t1 a 11/30/01 a1 a2 bottom view side view top view n t y r u c o l1 xx e1 d1 e e d b notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances , datums, etc. 2. the top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. dimensions d1 and e1 do not include mold protrusions. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions, including mold mismatch. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maxim um b dimension by more than 0.08 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages. 5. these dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. a1 is defined as the distance from the seating place to the lowest point on the package body. common dimensions (unit of measure = mm) symbol min nom max note 100t1 , 100-lead (14 x 14 x 1.0 mm body), thin plastic quad flat pack (tqfp) a1 0.05 0.15 6 a2 0.95 1.00 1.05 d 16.00 bsc d1 14.00 bsc 2, 3 e 16.00 bsc e1 14.00 bsc 2, 3 e 0.50 bsc b 0.17 0.22 0.27 4, 5 l1 1.00 ref
i 5665b?usb?04/05 AT76C713 table of contents features................. ................ ................. ................ ................. .............. ............ 1 1 overview ............ ................ ................ ............... .............. .............. ............ 2 2 AT76C713 functional diag ram ............. .............. .............. ............ .......... 3 3 pin diagram ........... .............. .............. ............... .............. .............. ............ 4 3.1100-pin tqfp package .............................................................................................4 4 pin summary ? pin assignment ............. ................. ................ ............... 5 5 signal description .............. .............. ............... .............. .............. ............ 6 6 functional description ............ ................ ................. ................ ............... 9 6.1bootstrap rom and programming modes ................................................................9 6.2avr core ................................................................................................................12 6.3oscillator and clock generator ...............................................................................13 6.4memory map ...........................................................................................................14 6.5memory access interface ........................................................................................15 6.6usb dma controller ...............................................................................................19 6.7usb controller ........................................................................................................20 6.8uart0, uart1 .......................................................................................................28 6.9irda 1.0 codec ........................................................................................................30 6.10watchdog timer ....................................................................................................31 6.11serial peripheral interface (spi) ............................................................................31 6.12jtag interface and on-chip debug system .........................................................34 6.13ieee 1149.1 (jtag) boundary-scan ....................................................................38 7 i/o space (register description) .................... .............. .............. .......... 45 7.1timers/counters ......................................................................................................54 7.2timer/counter 0 and timer/counter 2 .....................................................................55 7.3timer/counter 1 ......................................................................................................59 7.4watchdog timer ......................................................................................................62 7.5spi interface ............................................................................................................63 7.6i/o ports ...............................................................................................................64 8 memory space (register descr iption) ........... .............. .............. .......... 70 8.1usb register set ....................................................................................................70 8.2uart register set ..................................................................................................82 8.3memory access interface register set ...................................................................93
ii 5665b?usb?04/05 AT76C713 9 errata ............. ................ ................. ................ ................. .............. .......... 95 10 electrical specifications ................... ............... .............. .............. .......... 96 10.1absolute maximum ratings ...................................................................................96 10.2d.c. characteristics ..............................................................................................96 10.3ordering information .............................................................................................97 11 packaging information .......... .............. .............. .............. .............. ........ 98
printed on recycled paper. 5665b?usb?04/05 ? atmel corporation 2005 . all rights reserved. atmel ? , logo and combinations thereof, avr ? and dataflash are registered trademarks, and everywhere you are sm are the trademarks of atmel corporation or its subsidiari es. other terms and product names may be trademarks of oth- ers. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. atmel?s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imagin g/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature

▲Up To Search▲

Price & Availability of AT76C713

	To Download AT76C713 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .